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- เผยแพร่เมื่อ 30 พ.ค. 2024
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How Block RAM (BRAM) works inside of an FPGA for beginners. Learn about when and where you would use BRAM. Learn about different configurations: Single Port, Dual Port, FIFO. How are Block RAMs useful in crossing clock domains.
Shows how to instantiate, infer, and create BRAMs via the Interactive GUI, used in both VHDL and Verilog.
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Nice explanation. Just ordered the go board yesterday. Can't wait to get started.
I am learning BlueSpec and have to do a exercise where I need Block Ram. I had no idea what this is so thank you for this video :)
Really love this, thanks a lot
thank you it was usful , i wait for more details of other components in FPGA , thanks
Awesome video! Thanks for explaining on BRAM in detail.
Wonderful explanation 👏👏👏
great explanation again
keep them comin'!
Very concise! Thank you :)
Awesome vedio, thanks a lot!
Loved it ! So clearly explained.Thank you. Would be helpful if you explain stuff with Intel FPGAs
Hi Russel
Could you please create some BRAM examples on EDAplayground that could then be migrated to the GOboard.
Hello I like your videos, could you put a link of the power point of the video to let download it please?
Could you give an instance to initialize the bram module on new blank verilog project. So, i could store some data in it. Thanks bro
amazing, thanks
Thanks much appreciated
Hello Sir, can you please make a video how to store the text file in block RAM.
thank you for your help i understand verlog from your channel just
Thank you.
Thank you
Thanks for your video,but I don't really understand the first two ways of generating a BRAM at around 12:39.It would be much better if you can describe it using some more specific instances,such as code snippets or showcasing it yourself. Still,this is an awesome video,best regards from China.
Nice video
Is there any FPGA verilog example of reading and writing BRAM?
thank you for your tutorial. I'm desperately looking for an example or tutorial for block RAM instantiation. do you have one please? Thanks
Try working on some examples related to VGA. Those examples usually use block RAM's and you will also get a chance to practice. Another way to practice is to create a GCD calculator using (datapath+controller) and try feeding the design values from a ROM.
Thanks for the video, I have a question.
You mentioned at the end of video, BRAM is not recommended for large design.. then what is another option for large design?
I think I said that I don't recommend using the interactive GUI for creating BRAM for large designs. That's when I'm talking about what method to use to create the BRAM.
Ah, I misunderstood. Sorry. Then, What do you recommend to create BRAM? Sorry for silly question. I am a beginner of FPGA
For beginners/small designs I DO recommend the GUI tool. Large designs though it becomes unwieldy.
I am not able to wrap my head around what exactly makes, a BRAM. Since BRAM has variable width and depth, does it mean each and every bit of it is independent and addressable?
Hi Russel,
Could you tell me how to write a testbench for a BRAM of depth 50. I mean if the address we use for BRAM, Ex: bram(addr1) is more than 50 in terms of depth, how do you provide a 50-length long value for it in the testbench?
Thanks,
Varun
Hm not sure I understand the question. In general I set my depth to a base 2 number. 64, 128, 256 etc. That way the address is always valid.
Nice!
Amazing
I have one question. If I made '8bits width' and '1024 depth' BRAM, than whole size of memory that I made is 8*1024bits??
Yes
Thanks
Hi ! I am working on a program where I use your UART_RX and UART_TX to write back and forth to my MAC. But I want to save state on the fpga between reads and writes. For example, to calculate the sum of numbers arriving on the UART_RX then send the sum back to the MAC on the UART_TX. Can I put the "sum" variable in bram and still maintain state ?
BRAM is used for large amounts of data. "sum" is probably just a 16 or 32 bit register. That's small enough that it can go in normal register space. If it's > 1kb of memory then that's when BRAMs make sense.
@@Nandland Thank you for responding so quickly. 8-) Ok. So I am using your uart.v code with UART_RX and UART_TX. Between the two subroutines I stuck another subroutine that is called like this
CHANGE SMALL (.a(w_RX_Byte), .b(o_Byte));
and then o_Byte is passed to UART_TX.
The subroutine I use is called change.v and looks like this:
module CHANGE
(
input [7:0] a,
output reg [7:0] b
);
always @(*) begin
sum
Ahhh, a small glimmer of understanding....
I was not using the correct architecture for passing in the full byte from UART_RX to my
module. Inputs to a module are always wires. Outputs must be wires if they are
going to be passed along to another module...
can provide info about how to store pixel of a pic into bRAM
That was very informative..Sir I have a doubt.. Suppose Ihave a textfile and wanted to take its contents and store in this Block Ram.. is that possible?
Yes definitely, assuming the fpga itself supports this. You should be able to Google some examples of this.
why do you want 1
I didn't write code for this... so any example code that I show I didn't personally create. However this looks like just a way to create a variable length memory. 1
can you please make a video on distributed ram used in ultrascale fpgas and explain it in detail. thanks. awsm video
GREAT
Block RAM or BRAM is a type of random access memory embedded throughout an FPGA for data storage. You can use BRAM to accomplish the following tasks, Transfer data between multiple clock domains by using local FIFOs. Transfer data between an FPGA target and a host processor by using a DMA FIFO
Thanks for the video, but you said that creating block of RAMs using interactive GUI is not recommended. Personally, I disagree with you and I think that depends on the manufacturer of the FPGA. I use xilinx core generator and I can see that it provides optimal solutions for many designs
I recommend it for beginners. But I've worked on projects with 50+ independent Block RAM GUI created cores. It's a nightmare. I prefer inferring them when possible as you get more comfortable with FPGA design.
poor quality