ZYNQ AXI Interfaces Part 1 (Lesson 3)

The Xilinx ZYNQ Training Video-Book, will contain a series of Videos through which we will make the audience familiar with the architecture of the ZYNQ device. Then, we will teach how one can design embedded systems for the ZYNQ using the Vivado environment.

[@user-lo4er8wy9l]

The pace is just right for my brain to keep up.

[@statinskill]

bees knees -- I'm sorry to hear that because this guy was boring the crap out of me in the first minutes. I know how a bus works generally, I know what a bus master is. Anybody who even just casually plays around with Zynx SoCs knows that. What I don't are AXI specifics, how to generate the AXI interface on the PL side and also work it from that side.

[@nimasajedi1818]

TRM part description was absolutely fabulous. Actually, with understanding this part you are able to create your own system. Thank you very much dear Dr. Sadri for your effort to share your knowledge.

[@linuszoe9145]

You are a magician make difficult things easy. I really appreciate it!

[@weijiejiang2436]

Wish I can watch all of them 3 years ago. Really good intuitive videos!

[@patriotik]

You did a superb job with this, thanks.

[@thodorisbarbakos3982]

this lesson is what i need! Congratulations!!!

[@nimasajedi1818]

I watch each and each of your videos and they are really really helpful.

[@sivateja603]

Shelden Cooper bro.. great lecture and good clarity.. Thanks a lot!!

[@hiteshmandliya3960]

Great Video to Learn Zynq FPGA, Nice explanation and Dr. Mohammad has very good skills to explain in simpler manner.

[@posedgefarhan9497]

Very helpful Dr. Sadri. Thank you for making these wonderful videos

[@SandipDasprince5290]

This is indeed a Great Tutorial....!! Thanks a lot for posting this.!

[@jamesgreen4999]

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[@JoseFernandez-yz1sf]

Very informative video, many thanks

[@user-uf5gs9uj3j]

This video is so useful! I really appreciate it

[@mehmetburakaykenar]

thanks for videos, very good presentation and explanation

[@SciHeartJourney]

If you start finding this video confusing, jump to 37:00 for inspiration and the overview.
I've tried reading UG585 on my own and it's rather daunting. This video made it easier to understand, even though it's still a bit confusing. Thank you!

[@ahmadaudi7340]

Thank you so much, its very helpfull

[@duyoan1555]

Thank you so much for your helpful lesson

[@imadventure3351]

Thank you for very helpful lecture

[@morrison232]

Well done.

[@bINbih1]

Thank you

[@conne3554]

great thanks

[@mohamedyassin7806]

Dr.Mohamed Great thank for your help

[@tomzhu8719]

gooooooooooooood video

[@moustafaali3555]

thanks a lot

[@francescoesco123]

I love you

[@shv47]

At about 9:25 there is a mistake u said master sends ready signal but I think slave should be ready for data write.

[@EMSUNIKL]

Yes, you are correct. My fault. Thanks for the notation.

[@ChiragHadiya]

Why there is no read reasponse channel in axi ?

[@whattechtalk3823]

what ’s name the book？

[@vivekraj2984]

24:51 System diagram

[@mohithkumar3522]

9:07 who came in?

[@aienbalosaienbalos4186]

:D