Thank you. This tuturial is excellent. I would happily pay over $2400 (US) for Vipin Kizhepatt's course if he ever offered one! I mentioned $2400 because that's how much Xilinx wants for their training.
You have to pay more for university course which is even worse than Xilinx training, not to mention Vipin Kizhepatt. The only disadvantage is that the course is out-of-date and terrible accent (the same disadvantages exist in university course).
@@hengzhou4566 how is it out of date the zynq board he's working on is like 10 years old and the videos only 3-4 years old, coming to the accent is it really that bad to understand?
The work you have done by uploading the lectures in a great thing and helps the students to understand the Vivado well !! Could you please tell your system configuration where it is very fast in simulating ? Thank You for all you effort sir It means a lot to share such a knowledge
A great tutorial! Thank you for your effort. I am very sad to see that you have gone away 1 years ago. I hope you will come back again. I would be very pleased if you can write if you are planning to come back and upload any other videos in the future. Thank you.
Excellent tutorial sir. Thanks for taking so much efforts. Can you please make such video on APB protocol. If it's already there can you please share the link.
The name of the signals change slightly after synthesis, sometimes you can not find the exact node that you are looking for. So this method has limits.
Hello ,Sir I am working on a project related to FFT and require to give 32 bit inputs and observe 32 bit outputs.Could you please help me with pin assignments.
ILA is also implemented using FPGA logic. So as the number of signals and number of samples increases, the possibility of timing violation also increases.
Very awesome explanation sir. Each and every thing explained in great detail. Thank you so much.
Thank you so MUCH for your great video and explanation!!
It really helps A LOT to do my work and thesis !
I have no idea this feature existed~Thanks! This is extremely useful!
Thank you. This tuturial is excellent.
I would happily pay over $2400 (US) for Vipin Kizhepatt's course if he ever offered one!
I mentioned $2400 because that's how much Xilinx wants for their training.
You have to pay more for university course which is even worse than Xilinx training, not to mention Vipin Kizhepatt. The only disadvantage is that the course is out-of-date and terrible accent (the same disadvantages exist in university course).
@@hengzhou4566 how is it out of date the zynq board he's working on is like 10 years old and the videos only 3-4 years old, coming to the accent is it really that bad to understand?
Great work sir!
thank you for the video. great demonstration.
The work you have done by uploading the lectures in a great thing and helps the students to understand the Vivado well !!
Could you please tell your system configuration where it is very fast in simulating ?
Thank You for all you effort sir
It means a lot to share such a knowledge
Some times I make things faster in video editing. But my laptop is somewhat powerful. It is Lenovo Legion Y520 (i7, 16 GB RAM, NVidia GTX 1050)
Really helpful. Thanks to you.
Nice explanation.. sir.
Thank you.
Very helpful video, Sir.
Could u please add more videos on timing constraints
A great tutorial! Thank you for your effort. I am very sad to see that you have gone away 1 years ago. I hope you will come back again. I would be very pleased if you can write if you are planning to come back and upload any other videos in the future. Thank you.
YOUR AMAZING ! GREAT GREAT CHANNEL ! THANK YOU VERY MUCH !
Thank you so much 🙏🏻 For your amaizing Tuto
thank you very much.....nicely explained.
thank you very much, really useful
Nice tutorial!
Thanks! The video helps me.
Very helpful
Thanks
Excellent tutorial sir. Thanks for taking so much efforts. Can you please make such video on APB protocol. If it's already there can you please share the link.
APB I don't have any since none of the Xilinx IPs have APB interface. They all have only AXI4(full,lite or stream)
@@Vipinkmenon Thank u sir. But APB is used in industry right? So can study it right.
Yes of course. APB and AHB are widely used in ARM-based system design
@@Vipinkmenon Ok..thank u sir..Can we plz ask you if some code related problems are there on ur mail.
Yes sure
The name of the signals change slightly after synthesis, sometimes you can not find the exact node that you are looking for. So this method has limits.
Can you upload a video to TH-cam for free for debugging methods that has no limit?
Thanks
Can I implement this code in xilinix vivado to interface xadc with nexys A7 FPGA
Hello ,Sir I am working on a project related to FFT and require to give 32 bit inputs and observe 32 bit outputs.Could you please help me with pin assignments.
if no.of IOs are more then how to implement it on hardware sir?
Hi Professor. Thanks for the tutorial. The ILA debug core is showing timing violations. Hold violations. What could be the reason be? Any idea?
ILA is also implemented using FPGA logic. So as the number of signals and number of samples increases, the possibility of timing violation also increases.
I have one question ,i created my own module to divide clock but its not showing in ila