You're doing the Lord's work here! I'm not to FPGAs yet, but I keep studying them for when I move on from STM32. Your videos are invaluable for circuit design, generally, and not just FPGA. I'm so grateful for your presence in our lives!
Although I've worked in electronics for over a decade, this year I designed my first PCB and just for a personal project. I've come to enjoy the process of laying out, it feels like SimCity did back in my youth.
This is why we love your content.... where else on TH-cam do we have this indpeth look at PCIe interfaces and stuff! I'm never gonna build a pcb with one, but its seriously interesting to learn about all the same! This stuff, combined with your DSP theory with practical examples has just been a gold mine of 'intresting' content (for me, but for others, a seriously useful resource for future work!). Thank you!
Dude, you are literally the best TH-cam channel I have ever seen, I wonder if Dave from EEVblog follow you, your audiences are pretty much the same, I'd think. Anyways, your videos helped me a lot getting into the design of electronics. Now I'm working with the development of instrumentation, sincerely a physicist.
Thank you very much, Luiz! I've spoken to Dave before but not sure if he actively follows the channel. There definitely should be some audience overlap :) Glad to hear that the videos have been helping you get more into electronics!
I second that. A good way to complete the board would be some PCIE driver code on the host, and finally the necessary implementation on the FPGA itself. I remember PCIe had some required registers to implement but the overall architecture is a little fuzzy to me. A complete guide would be invaluable!
This is probably the single most interesting / inspirational form factor / interface for FPGA dev - as you can slot it in to so many devices, from Windows laptops to RPi SBCs, etc, etc. I'd like to thank you for the video and add my voice to the comments below asking how you access the FPGA via software - the PCIe driver, etc.
“Phil’s Lab” needs a “Phil’s Kit” store so your loyal subscribers can purchase the products of your hard work. A year ago I hardly knew anything related to electronics, RF, etc. Your channel has played a huge part in bringing me into the light. Great content, fast paced, very watchable. I hope you take some time to sleep. Thanks for the videos
Thank you very much for your kind comment, Jason! Awesome to hear that the videos have helped out on the electronics side. For now, the courses are all I'm offering in my "Phil's Kit" store I'm afraid. Selling hardware would probably mean even less sleep :D
@@PhilsLab I plan on taking a few of your courses in the near future. I really want to try to taking something from idea to finished product. That being said, what do you think of the feasibility of using an M.2 slot as the dedicated interface for an RTL-SDR receiver? Or , beyond , as the interface for a “yet to be named” SDR transceiver? I have a list of questions but I’ll leave them for another time. Thanks for all the great content and for taking the time out of your busy schedule to respond to your viewers comments and questions. Hardly any of the Channel owners do anymore. Thanks again!
When the project is completed, maybe consider making that FPGA M2 accelerator available as an "off the shelf" product on Farnell or other electronics distributors. Currently, there is no cheap hobby/home use FPGA accelerator. The closest to that would be Digilent's Arty7 (at about 170 euros) but it's rather a development board than an accelerator. Make it easy for the host CPU to communicate with it, and a lot of coders will have tons of fun doing some Verilog or VHDL with it ! :)
@@oliverer3 I'd get it for 200-250 bucks. 300-400 is strechind it, but I'm a cheapskate. It looks like a great IC development board even if you're not using it for accelerating any workloads from the host system.
you guys dont know about the sipeed tang series? tang nano 9k is like 20€ and can already do quite a lot of stuff. highly recommend. the nano 20k is bigger and has a nice development kit for like 60€.
Litefury and nitefury-II are basically same thing but with a huge A7 (100 and 200 respectively iirc) . Both on Amazon for under $160 or so - which is less than a raw A200 chip would cost !
Hi Phil, I watched through every single of your video. You teased this board in a previous video and I searched for it almost everywhere but could find. Glad you published this video
Wow, you are a god and a genius. Would like to make this someday to off load AI/ML acceleration tasks. I read many papers stating that FPGAs are much faster in matrix multiplication than GPUs even with tensor cores. This design would save so much time in brainstorming to design one. Thanks. Edit: Thank you for making a FPGA high speed course, I have been looking on google and no such course exits, will definitely join the course.
Judging by Phil's progress since I subscribed, in two years, I expect to see a video on how to design a smartphone board or something for a space satellite.
Will there be a video on the software side of things? It would be interesting to get an overview of the PCI-E driver and other software parts on the host side.
I must say, this video is excellent, you explain your process of thinking quite well, and throw in nuggets of information that is quite useful. Right on man, keep it up!
Depending on your FPGA's BGA pitch, if you use round pads on the bottom you can fit 0402 decouplers between the pins. This allows more to be located where you'd prefer them. Good video. 👍
Love the tag connect programming headers, we use the 6 and 10 pin versions for various MCU and FPGA designs. They even have a “legless” version so you don’t have to route around the leg mounting holes
The Tag Connect stuff is great! I used the 'legged' version here, as the no-leg retainer clip on the back wouldn't fit when then board is in the M2 socket.
This is fantastic! I would love to see a video designing around the coral/google TPU edge accelerator. I think it would be quite difficult since you need a 64 bit processor running embedded linux.
Last year I had to design my first ever board, and it was going to be populated with this exact FPGA. I was thrown in the deep end suffice it to say haha, wish this video existed then. Also unrelated but still related, your videos in general have helped and taught me so much since I found your channel last year! Keep doing the lords work man 👍
Thanks a lot for your highly professional experience sharing. It is rare in TH-cam. For sure, Altium Academy rocks, but nice to see also user experience. As HW developer, I know how many discussions and best practice sharing could be in this field.
Amazing. This is way, way, way out of my league, but you made it interesting despite me not knowing what was going on most of the time. It blows my mind that people are this smart.
mPCIe also includes a USB2 connection on the card edge connector (And even has pins for SIM-cards to be used, in the case of cellular modems.). I'm not sure if they could be used simultaneously. So, if you plan on ever doing a re-revision of your PCB, you might be able to put a USB to JTAG bridge directly on your board for programming and debugging while the card is installed, without needing an external JTAG interface unless you're doing extremely high speed stuff.
That would be a nice solution but again you will be limited by the number of pcie lanes since mPCIe provide x1 lanes and this card is designed with x4 pcie lanes
Hello Phil! Is it possible to have a power-on sequence as follows? VCCINT -> VCCBRAM -> VCCAUX -> VCCO -> VMGTAVCC -> VMGTAVTT I couldn't find a proper answer in datasheets and forums.
Hey Phil, awesome video again. Can I ask how you program this device/interface with PC? Would love to see a video of what exactly this device is intended to do in the PC environment.
For a few minutes, I thought this is Phil's Computer Lab... and was wondering why the voice is a bit different, and is the FPGA going to be used for retro emulation acceleration or something....
Interesting board and loads of useful information and tips as always! The board reminds me of the Acorn CLE-215 which was intended for some crypto mining application but never took off. I think it had an Artix7 200T and were apparently available cheap on ebay a few years back although I've never managed to get my hands on one. People did some quite interesting things with them including running LiteX RiscV designs.
I'm very much a noob in electronics so pardon the dumb question: 7:00 isn't the pull-up resistor (R203) setting the PG1 to normally high already? so wouldn't it be permanently enabling EN2?
Thank you so much. How can i rout between DDR3 IC MT41K128M16JT-25:K and ZYNQ FPGA XC7Z020-2CLG484i ? And how can make sure their signal and power integrity are valid and work properly. Thank you in advance ❤
Hey phil, how do you find this pin propagation delay for this fpga? Im designing a similar board and i try to check in the ibis model but i dont find it. Nice board btw!!
This looks like a very, very good layout. Great work! The only place I would have made some extra effort is on the feedback of the DC/DC converter. As it's working at very high Fcy (>2MHz), feedback will be VERY sensitive to noise. A star connection to pin 24 "Analog Ground" can help reducing sensitivity to noise. Even more important when you're doing railway/military/automotive designs sitting in high EM fields environment.
I just started your Mixed signal IC course, and I'd love an FPGA hardware design. The most I've done with FPGAs is HDL (Verliog/VHDL), but it would be awesome learn how they are designed as well!
Thank you so much for your exhaustive tutorials Phil ... Keep up the nice work you're doing for the TH-cam electronic community... To ♾️ and "so forth" 😅❤
Hi Phil, will you be covering the software stack for communicating with the FPGA from Linux or Windows? I think that's also a fairly important aspect of custom FPGA hardware accelerators in commodity laptops/PC's. Thanks.
Nice design! Did you create the schematic symbol of the artix 7 by yourself? Especially the decoupling networks are very clean. I don't really like the power page, it's kind of unstructured. Greets from a hw dev.
Excellent video, as are your others. How do you decide on whether to terminate DDR3 address lines or not? I've seen it done and not done (on reliable products), and conflicting information, so erred on the side of caution when I had a project on a tight timeline. This added cost for the Vtt rail and power dissipation so I would have liked to omit. Thanks.
Very nice! I remember wanting to do something like this as well, but then I've decided to not risk it and got a dev kit from Terasic\Intel Instead. I've got a few questions - 1. Is it possible to simulate the board before sending it to production? Is it possible to verify that the pcie is in spec and do some kind of assertions with the custom chips (fpga in this case) to check if the important \ non-configurable lines are okay? 2. What about heat? I mean, it's a nice form factor and all, but is it possible to know how much heat that thing is going to produce before finding out that your PC is melting from the inside? 3. How fast can you go? I mean, what are the limitations of using a service like PCBWay when it comes to fast hardware implementation such as this (pcie, ddr memory)? will there be a bottleneck if, hypothetically, I'll come across a really fast FPGA chip that would usually be bundled with really fast memory such as DDR5 and have the parts matched using a service such as this, or is there a 'sweet spot' I should stick to when it comes to making my own design? I don't really know what makes a pcb good for high speed computing, no idea how to get the settings right when ordering or how to tell if a supplier isn't capable of delivering the right quality of the board I need. 4. Will you touch the programming part? I'd love to see you configure something like this, so it's able to 'talk' with other parts of the system - like getting it to output using the network card for debugging \ data instead of running physical wires, assuming it's going to be used inside some kind of a computer - lots of built in outputs and not much space for actual wires.
I was happy with my laptop, loved it. Single M.2 slot, all I needed. And then I saw this... Now I need a newer laptop, with second M.2 slot. You rotten swine, you (reference to classic radio comedy, The Goon Show)
It would be very niche, and it’s pretty difficult to balance offload perf improvements with added IO latency. I wonder if this was a more of an exercise than something with a concrete use in mind?
I typically match all signals within a group - overall, it isn't too much extra effort. However, you should be able to get away with not matching some signals as strictly (NCS and NRESET). Check out NXP's AN3940 for example or Xilinx 7 Series PCB Design Guide for more detail.
Hi there, huge fan of your content. I do have a question however. Did you already test the DDR3 interface? I am designing my first board with a DDR3 memory and a 7-series FPGA, and am a bit skeptical about omitting the termination resistors, which I technically can, given I am also only using one DDR memory chip.
Very cool board! I was looking for something exactly like this for prototyping and playing around and found nothing about a year ago. $1k is a bit more than I'm comfortable with to just play around. Have you considered a kickstarter? What would the price be in quantity of say 50 or say 200?
Thanks, Nicolae! I need to double-check what the board would run at higher quantities - however, I can't source any more of the Artix FPGAs :( A Kickstarter would have to wait until this chip shortage has blown over I'm afraid, but I'd love to do one at some point.
This is really cool, nice discussion and documentation of the PCB design, the electronics design community definitely lacks this. What kind of projects do you think you could use this for ?
Amazing! Would it be possible to get the sources for this? Would be useful to use it unmodified for some purposes. If you want/need help, I can help with the Linux driver side, or even simpler testing with memory maps without the driver initially - I've previously worked with Xilinx Spartan 6 and Zynq, and Altera Stratix IV devices.
Do you know if there's a way to set up an Altium DRC rule for requiring reference vias within a certain distance of a via in a particular net class? Is the DRC query language smart enough to be able to also check if the signal via's layer range (in blind/buried boards) is a subset of the reference via's layer range? e.g. a via from 1:2 shouldn't be considered a valid reference via for a signal via from 3:6.
Love the DDR layout! Man though, if I could find some way to actually get my hands on FPGAs as a hobbiest that would be awesome, unfortunately I have to rely on work to buy me toys for now. Where did you source your A7?
This hardware screams out for an open source HDL design for partial reconfiguration of the 7-series FPGA over PCIe. Do you know of an example project that does that?
I've done this for the Artix 7 75T. It's referred to as Tandem with Field Updates. It's a very advanced FPGA design methodology, so I wouldn't recommend attempting unless youre familiar with FPGA development. There are example projects included with the PCIe IP in Vivado.
The next thing I would ask you if that was able to have that kind of setup could you just get a SSD based PCI Express board that has multiple spots for the ssds towards to put more than one of these processor accelerators onto it?
Future video suggestion... plugging in, powering up and using FPGA + PCIe board, drivers, software tool chains for programming the FPGA. Several use cases: ML use case, offloading compute, system monitoring of compute time reduced compared to no FPGA... board cost compared to other manufacturer equiv FPGA chip...
Thanks for this amazing video. Although I usually stay away from Xilinx FPGAs, I might try to design along using an STM32MP157. By the way, when you order these boards, isn't it a customs nightmare to import? I'm asking because so far I had to keep everything below 150EUR to have a quick and un-problematic shipping.
Thanks for watching! Regarding import - you can either use DDP shipping (if offered) where you prepay charges. Or just pay customs when it arrives in your country - if you have set up a business it makes it a bit easier with VAT/EORI numbers.
What's a real world use case where a 60 layer PCB would be used? The biggest I've ever seen was a small form factor dual socket motherboard with 16 layers and that seems crazy.
Hello - for propagation delay - exporting values from Vivado are for example in this format Min Trace Delay (ps) Max Trace Delay (ps) A10 RSVDGND 27.853 28.133 A3 GNDADC 31.635 31.953 A4 VCCADC 30.131 30.434 A6 VREFP 27.116 27.389 A7 DXP 20.476 20.682 A8 M0_0 25.429 25.684 Would really want to understand how to use above min/max from Vivado in Altium Thanks
Having done pretty heavy developpement with Xilinx Virtex 6 FPGAs for some years I can confirm this guy knows what he does! A very nice board man 👍
Thank you very much - glad you approve! :)
Facts. Dude is a real computer engineer nerd, gotta admit it.
@@PhilsLab : Heh...some of us know what you are doing there. I just wish I had another M.2 slot on my machine to run with a toy like this.
this guy fucks!
What was your Virtex 6 FPGA application?
You're doing the Lord's work here! I'm not to FPGAs yet, but I keep studying them for when I move on from STM32. Your videos are invaluable for circuit design, generally, and not just FPGA. I'm so grateful for your presence in our lives!
Thank you very much for watching! :)
Although I've worked in electronics for over a decade, this year I designed my first PCB and just for a personal project.
I've come to enjoy the process of laying out, it feels like SimCity did back in my youth.
This is why we love your content.... where else on TH-cam do we have this indpeth look at PCIe interfaces and stuff!
I'm never gonna build a pcb with one, but its seriously interesting to learn about all the same!
This stuff, combined with your DSP theory with practical examples has just been a gold mine of 'intresting' content (for me, but for others, a seriously useful resource for future work!).
Thank you!
Thank you very much for your kind comment! Glad to hear that also the mix of different subject areas is of interest :)
Dude, you are literally the best TH-cam channel I have ever seen, I wonder if Dave from EEVblog follow you, your audiences are pretty much the same, I'd think.
Anyways, your videos helped me a lot getting into the design of electronics. Now I'm working with the development of instrumentation, sincerely a physicist.
Thank you very much, Luiz!
I've spoken to Dave before but not sure if he actively follows the channel. There definitely should be some audience overlap :)
Glad to hear that the videos have been helping you get more into electronics!
I’d be really interested in your implementation of the host-side pci driver. Will you be covering this on the channel?
I second that. A good way to complete the board would be some PCIE driver code on the host, and finally the necessary implementation on the FPGA itself. I remember PCIe had some required registers to implement but the overall architecture is a little fuzzy to me. A complete guide would be invaluable!
Yes, I'll do that once I've written and tested the implementation!
@@PhilsLab Awesome, looking forward to it!
Xilinx provides some pretty well done drivers stock, and they work with their free IP cores!
Just be aware that while booting the system you need to have a PCIe core running inside the FPGA so that BIOS can detect the card.
Glad to see my M.2 footprint templates were useful. That is a really cool board you made there!
This is probably the single most interesting / inspirational form factor / interface for FPGA dev - as you can slot it in to so many devices, from Windows laptops to RPi SBCs, etc, etc.
I'd like to thank you for the video and add my voice to the comments below asking how you access the FPGA via software - the PCIe driver, etc.
“Phil’s Lab” needs a “Phil’s Kit” store so your loyal subscribers can purchase the products of your hard work. A year ago I hardly knew anything related to electronics, RF, etc. Your channel has played a huge part in bringing me into the light. Great content, fast paced, very watchable. I hope you take some time to sleep. Thanks for the videos
Thank you very much for your kind comment, Jason! Awesome to hear that the videos have helped out on the electronics side.
For now, the courses are all I'm offering in my "Phil's Kit" store I'm afraid. Selling hardware would probably mean even less sleep :D
@@PhilsLab I plan on taking a few of your courses in the near future. I really want to try to taking something from idea to finished product. That being said, what do you think of the feasibility of using an M.2 slot as the dedicated interface for an RTL-SDR receiver? Or , beyond , as the interface for a “yet to be named” SDR transceiver? I have a list of questions but I’ll leave them for another time. Thanks for all the great content and for taking the time out of your busy schedule to respond to your viewers comments and questions. Hardly any of the Channel owners do anymore. Thanks again!
When the project is completed, maybe consider making that FPGA M2 accelerator available as an "off the shelf" product on Farnell or other electronics distributors. Currently, there is no cheap hobby/home use FPGA accelerator. The closest to that would be Digilent's Arty7 (at about 170 euros) but it's rather a development board than an accelerator. Make it easy for the host CPU to communicate with it, and a lot of coders will have tons of fun doing some Verilog or VHDL with it ! :)
Difficult to make it cheap, especially small scale.
That FPGA alone is a €100 part.
@@oliverer3 I'd get it for 200-250 bucks. 300-400 is strechind it, but I'm a cheapskate. It looks like a great IC development board even if you're not using it for accelerating any workloads from the host system.
you guys dont know about the sipeed tang series? tang nano 9k is like 20€ and can already do quite a lot of stuff. highly recommend. the nano 20k is bigger and has a nice development kit for like 60€.
Litefury and nitefury-II are basically same thing but with a huge A7 (100 and 200 respectively iirc) . Both on Amazon for under $160 or so - which is less than a raw A200 chip would cost !
@@はいこれはロボ子の婚約者I find that the speed with which Tang builds bitstreams is INSANE. Designs that take 15 min in vivado are done in 70 sec in gowin
Hi Phil, I watched through every single of your video. You teased this board in a previous video and I searched for it almost everywhere but could find. Glad you published this video
Wow, you are a god and a genius. Would like to make this someday to off load AI/ML acceleration tasks. I read many papers stating that FPGAs are much faster in matrix multiplication than GPUs even with tensor cores. This design would save so much time in brainstorming to design one. Thanks. Edit: Thank you for making a FPGA high speed course, I have been looking on google and no such course exits, will definitely join the course.
What a pleasure we are! 🥂
Your evolution video after video is impressive, great job!
Thank you very much, Thomas - hope it isn't downhill from here :D
Judging by Phil's progress since I subscribed, in two years, I expect to see a video on how to design a smartphone board or something for a space satellite.
@@km-electronics1 "...and here's how we construct the phased array antennas and microwave emitters to construct a simple Starlink like design"
What a beautiful board!
Thank you, Jonathan!
Do you mean Phil's engineering work or made-in-China PCB work specifically ?!...
Very neat components placement.
I wish I had more time to watch all your content. Genuinely. Please don't stop.
Thank you very much, Alexander!
1st King Philip's reality show :)
I can't wait to see the course.
Thanks for the great content.
keep up great work!
Haha thanks, Mustafa!
Wow, this is incredibly impressive. Well done! I'm in awe.
Thanks, Esra!
Will there be a video on the software side of things? It would be interesting to get an overview of the PCI-E driver and other software parts on the host side.
Yes, will be making videos on software/HDL side of things. Although that may be a while I'm afraid.
I must say, this video is excellent, you explain your process of thinking quite well, and throw in nuggets of information that is quite useful. Right on man, keep it up!
Depending on your FPGA's BGA pitch, if you use round pads on the bottom you can fit 0402 decouplers between the pins. This allows more to be located where you'd prefer them. Good video. 👍
Love the tag connect programming headers, we use the 6 and 10 pin versions for various MCU and FPGA designs. They even have a “legless” version so you don’t have to route around the leg mounting holes
The Tag Connect stuff is great! I used the 'legged' version here, as the no-leg retainer clip on the back wouldn't fit when then board is in the M2 socket.
This is fantastic! I would love to see a video designing around the coral/google TPU edge accelerator. I think it would be quite difficult since you need a 64 bit processor running embedded linux.
Thanks for the great content! My headache of choosing a buck converter is gone :)
Last year I had to design my first ever board, and it was going to be populated with this exact FPGA. I was thrown in the deep end suffice it to say haha, wish this video existed then. Also unrelated but still related, your videos in general have helped and taught me so much since I found your channel last year! Keep doing the lords work man 👍
Short but very informative, well done Phil, thank you.
Thank you, Emin!
Very impressive project and board 👏 👏 👏
Thank you, Nicola!
This is extremely helpful. Thanks! I will definitely be using your suggestions for my next project.
i have been looking for this type of work, this so clear to understand, great work👍🏻
Superb Video, signed up for your new course. Thanks Phil, your a breath of fresh air 🙂
Thank you very much, Dean!
Thanks a lot for your highly professional experience sharing. It is rare in TH-cam. For sure, Altium Academy rocks, but nice to see also user experience. As HW developer, I know how many discussions and best practice sharing could be in this field.
yes, congratulations! next a symmetric discombobulater! love the presentation!
Finally I love this since there's so much you can do with this
Amazing. This is way, way, way out of my league, but you made it interesting despite me not knowing what was going on most of the time. It blows my mind that people are this smart.
Thank you very much!
mPCIe also includes a USB2 connection on the card edge connector (And even has pins for SIM-cards to be used, in the case of cellular modems.). I'm not sure if they could be used simultaneously. So, if you plan on ever doing a re-revision of your PCB, you might be able to put a USB to JTAG bridge directly on your board for programming and debugging while the card is installed, without needing an external JTAG interface unless you're doing extremely high speed stuff.
That would be a nice solution but again you will be limited by the number of pcie lanes since mPCIe provide x1 lanes and this card is designed with x4 pcie lanes
These are the videos that have to reach millions of views. I can't wait to get started with FPGAs. Still find them intimidating.
There's definitely quite a steep learning curve with FPGAs would very rewarding nonetheless!
Superb tutorial!
Thank you, Michal!
As always brilliant with tons of information. 😀
Thank you, Amaldev!
Hello Phil! Is it possible to have a power-on sequence as follows? VCCINT -> VCCBRAM -> VCCAUX -> VCCO -> VMGTAVCC -> VMGTAVTT
I couldn't find a proper answer in datasheets and forums.
This is amazing!!! Can't wait for your course
Thank you, Robby!
Niceee, this is what i’ve been waiting forr. Can’t wait to take the course.
Thanks, glad to hear that!
in my opinion, you are the best...by far.. thanks for sharing Phil 😄
Hey Phil, awesome video again. Can I ask how you program this device/interface with PC? Would love to see a video of what exactly this device is intended to do in the PC environment.
Great video Phil. Brilliant mate.
I wonder about benchmarks with and without hardware accelerator, drivers, and device manager. This is awesome.
For a few minutes, I thought this is Phil's Computer Lab... and was wondering why the voice is a bit different, and is the FPGA going to be used for retro emulation acceleration or something....
That's awesome. Now to figure out the PCIe IP block and drivers
Exactly :(
Interesting board and loads of useful information and tips as always!
The board reminds me of the Acorn CLE-215 which was intended for some crypto mining application but never took off. I think it had an Artix7 200T and were apparently available cheap on ebay a few years back although I've never managed to get my hands on one. People did some quite interesting things with them including running LiteX RiscV designs.
Kintex 7 325T! Also available from the original designer as a dev board.
Source: have both, they’ve been a great testbed but cooling is a nightmare.
This is amazing! Really nice job.
Thank you!
I'm very much a noob in electronics so pardon the dumb question: 7:00 isn't the pull-up resistor (R203) setting the PG1 to normally high already? so wouldn't it be permanently enabling EN2?
Regarding the PCIe lanes, under a ps, did you take in account the internal FPGA delays for them to actually match?
Thank you so much. How can i rout between DDR3 IC MT41K128M16JT-25:K and ZYNQ FPGA XC7Z020-2CLG484i ? And how can make sure their signal and power integrity are valid and work properly.
Thank you in advance ❤
Assume you'll have to write firmware and drivers for this, can you make videos on that topic too?
Yes, I'm planning to do that for FPGA and SoCs.
Woow excelent video! I was about to start studying for a developing a high speed board and this is great!
Thanks, Rafael :)
Awesome! So now we need a design of embedded linux with PCIe m2 slot where we can plug it!
60 layers 'Mental' indeed ! scary looking stuff...Cheers.
Hey phil, how do you find this pin propagation delay for this fpga? Im designing a similar board and i try to check in the ibis model but i dont find it. Nice board btw!!
This looks like a very, very good layout. Great work!
The only place I would have made some extra effort is on the feedback of the DC/DC converter. As it's working at very high Fcy (>2MHz), feedback will be VERY sensitive to noise. A star connection to pin 24 "Analog Ground" can help reducing sensitivity to noise. Even more important when you're doing railway/military/automotive designs sitting in high EM fields environment.
I just started your Mixed signal IC course, and I'd love an FPGA hardware design. The most I've done with FPGAs is HDL (Verliog/VHDL), but it would be awesome learn how they are designed as well!
Thanks for signing up to the course :) Hope the next course will address that!
Thank you so much for your exhaustive tutorials Phil
... Keep up the nice work you're doing for the TH-cam electronic community... To ♾️ and "so forth" 😅❤
Thank you very much, Muhammad!
Hi Phil, will you be covering the software stack for communicating with the FPGA from Linux or Windows? I think that's also a fairly important aspect of custom FPGA hardware accelerators in commodity laptops/PC's. Thanks.
Nice design! Did you create the schematic symbol of the artix 7 by yourself? Especially the decoupling networks are very clean.
I don't really like the power page, it's kind of unstructured.
Greets from a hw dev.
Excellent video, as are your others. How do you decide on whether to terminate DDR3 address lines or not? I've seen it done and not done (on reliable products), and conflicting information, so erred on the side of caution when I had a project on a tight timeline. This added cost for the Vtt rail and power dissipation so I would have liked to omit. Thanks.
Please let me know when the lecture starts. I really want to take it.
Very nice! I remember wanting to do something like this as well, but then I've decided to not risk it and got a dev kit from Terasic\Intel Instead.
I've got a few questions -
1. Is it possible to simulate the board before sending it to production? Is it possible to verify that the pcie is in spec and do some kind of assertions with the custom chips (fpga in this case) to check if the important \ non-configurable lines are okay?
2. What about heat? I mean, it's a nice form factor and all, but is it possible to know how much heat that thing is going to produce before finding out that your PC is melting from the inside?
3. How fast can you go? I mean, what are the limitations of using a service like PCBWay when it comes to fast hardware implementation such as this (pcie, ddr memory)? will there be a bottleneck if, hypothetically, I'll come across a really fast FPGA chip that would usually be bundled with really fast memory such as DDR5 and have the parts matched using a service such as this, or is there a 'sweet spot' I should stick to when it comes to making my own design? I don't really know what makes a pcb good for high speed computing, no idea how to get the settings right when ordering or how to tell if a supplier isn't capable of delivering the right quality of the board I need.
4. Will you touch the programming part? I'd love to see you configure something like this, so it's able to 'talk' with other parts of the system - like getting it to output using the network card for debugging \ data instead of running physical wires, assuming it's going to be used inside some kind of a computer - lots of built in outputs and not much space for actual wires.
I was happy with my laptop, loved it. Single M.2 slot, all I needed. And then I saw this...
Now I need a newer laptop, with second M.2 slot.
You rotten swine, you (reference to classic radio comedy, The Goon Show)
Can you show how you’d use this in a program? It’s very interesting but I have no idea how to put some hardware acceleration processing on that
It would be very niche, and it’s pretty difficult to balance offload perf improvements with added IO latency. I wonder if this was a more of an exercise than something with a concrete use in mind?
Pristine work, couldn't have done it better myself. That's what a proper hardware design should look like.
Thank you very much!
How did you set up the clocks in the MIG? Trying to do this myself and not sure what I should do about the system clock...
Hi Phil, should you provide the length matching only for data and CLK lines or for all interface signals including e.g. WE, CAS, CS...?
I typically match all signals within a group - overall, it isn't too much extra effort. However, you should be able to get away with not matching some signals as strictly (NCS and NRESET). Check out NXP's AN3940 for example or Xilinx 7 Series PCB Design Guide for more detail.
Hi there, huge fan of your content.
I do have a question however. Did you already test the DDR3 interface? I am designing my first board with a DDR3 memory and a 7-series FPGA, and am a bit skeptical about omitting the termination resistors, which I technically can, given I am also only using one DDR memory chip.
Very cool board! I was looking for something exactly like this for prototyping and playing around and found nothing about a year ago. $1k is a bit more than I'm comfortable with to just play around. Have you considered a kickstarter? What would the price be in quantity of say 50 or say 200?
Thanks, Nicolae! I need to double-check what the board would run at higher quantities - however, I can't source any more of the Artix FPGAs :( A Kickstarter would have to wait until this chip shortage has blown over I'm afraid, but I'd love to do one at some point.
This is really cool, nice discussion and documentation of the PCB design, the electronics design community definitely lacks this. What kind of projects do you think you could use this for ?
Does one of your courses show the process of making this board?
Amazing! Would it be possible to get the sources for this? Would be useful to use it unmodified for some purposes. If you want/need help, I can help with the Linux driver side, or even simpler testing with memory maps without the driver initially - I've previously worked with Xilinx Spartan 6 and Zynq, and Altera Stratix IV devices.
This is crazy! Can you imagine using it for fpga gaming on a laptop?
Nice! Thank you for the share.
- How much time did you spend on such design?
- Could you share also some testing results on the EMI side?
Thanks for the video, very informative!
Is it possible to download the project files for this lesson somewhere?
Do you know if there's a way to set up an Altium DRC rule for requiring reference vias within a certain distance of a via in a particular net class? Is the DRC query language smart enough to be able to also check if the signal via's layer range (in blind/buried boards) is a subset of the reference via's layer range? e.g. a via from 1:2 shouldn't be considered a valid reference via for a signal via from 3:6.
I'm pretty sure all of that is possible with custom 'DRC queries' in Altium. You can build pretty complex rules using the builder/helper.
Is there a reason why you use Polygons over split powerplanes? They make the board view a lot less cluttered
Love the DDR layout! Man though, if I could find some way to actually get my hands on FPGAs as a hobbiest that would be awesome, unfortunately I have to rely on work to buy me toys for now. Where did you source your A7?
When do you plan to release the Advanced PCB design course?
Nice design and nice outcome. Why don't you use the transparency features in the 2D board view? It could help you a lot in seeing a lot of details.
I wonder if it is possible to use for "emulators" for retro consoles like Mister.
When the course will be available?
This hardware screams out for an open source HDL design for partial reconfiguration of the 7-series FPGA over PCIe. Do you know of an example project that does that?
I've done this for the Artix 7 75T. It's referred to as Tandem with Field Updates. It's a very advanced FPGA design methodology, so I wouldn't recommend attempting unless youre familiar with FPGA development. There are example projects included with the PCIe IP in Vivado.
Beautiful 👍
Very Informative
Thanks, Mohsin!
Very nice... for the power supply what was your gain and phase margin for the stability analysis? Just curious
The next thing I would ask you if that was able to have that kind of setup could you just get a SSD based PCI Express board that has multiple spots for the ssds towards to put more than one of these processor accelerators onto it?
How do you decide which and how many layers are ground or power?
I'm wondering why you didn't just go for a differential clock for your design than a single ended one?
Future video suggestion... plugging in, powering up and using FPGA + PCIe board, drivers, software tool chains for programming the FPGA. Several use cases: ML use case, offloading compute, system monitoring of compute time reduced compared to no FPGA... board cost compared to other manufacturer equiv FPGA chip...
I would be really interested in the fpga programming and the software on the host Pc side
Thanks for this amazing video. Although I usually stay away from Xilinx FPGAs, I might try to design along using an STM32MP157. By the way, when you order these boards, isn't it a customs nightmare to import? I'm asking because so far I had to keep everything below 150EUR to have a quick and un-problematic shipping.
good point i am very curious too since china imports entering EU are sometimes problematic
Thanks for watching!
Regarding import - you can either use DDP shipping (if offered) where you prepay charges. Or just pay customs when it arrives in your country - if you have set up a business it makes it a bit easier with VAT/EORI numbers.
What's a real world use case where a 60 layer PCB would be used? The biggest I've ever seen was a small form factor dual socket motherboard with 16 layers and that seems crazy.
How many iterations of that $1000 order did it take & how much hardware acceleration did it achieve?
Hello - for propagation delay - exporting values from Vivado are for example in this format
Min Trace Delay (ps) Max Trace Delay (ps)
A10 RSVDGND 27.853 28.133
A3 GNDADC 31.635 31.953
A4 VCCADC 30.131 30.434
A6 VREFP 27.116 27.389
A7 DXP 20.476 20.682
A8 M0_0 25.429 25.684
Would really want to understand how to use above min/max from Vivado in Altium
Thanks
I wonder if I can do something like this with KiCad.
will you publish this design as open source hardware? hope you are doing so as you have your repo link underneath your video description.