Zynq Part 2: Zynq Vitis Example with PL Fabric GPIO and BRAM
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- เผยแพร่เมื่อ 7 ส.ค. 2023
- Hi, I'm Stacey, and in this video I go over part 2 in my zynq series, using Vitis!
Part 1: • Zynq Part 1: Vivado bl...
Github Code:
github.com/HDLForBeginners/Ex...
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Thank You! Really clear and detailed explanation. The best I've seen on TH-cam,
Thank you Stacey for taking the time to share this knowledge. Your explanations are really helpful.
Thank you very much, I'm totally new to FPGAs and tools but Part 1&2 helped me understand Zybo boards, Vivado and Vits. For your reference I used Zybo 20 with Vits 2023.2 (it is not on eclipse but on Vcode). But it is intuitive to find all the option. Although I didn't find xbram in the hardware this is a good start toggling SWs & LEDs.
thanks a lot for this detialed explanation, it helps a lot for beginners like me!
Completely useful and clear! Thank You
Thank you very much for these videos !
Really great video, should have more views
I hope you will keep going with the vide😢this videos are really informative
Best of TH-cam hands down… where did the uart come from though ? And the printf() function - is there some kind of rtl (as in runtime library) and a kernel behind the scenes ?
Hello . Very nice examples (vivado+Vitis). Can you do another part where the Bram is read/write from PL side concurrently from PS ? Than you for very clear explanation. Your video is very interesting for me. Ciao
See part 3, this is where I do read/writes from the PL as well.
excellent, very clear & practical tutorial. What doing the same thing using opensource tools
Thanks for the tutorial, Stacey! While I can follow the coding portion I am a bit lost on how to set up Vitis.
I am sure I have the Vitis IDE but it says unified IDE now, it seems like a new version. While I was able to create a project and a system I can't find this prj file or the BSP settings. When starting I get the options of creating either: platform components, embedded aplication or a system project, what should I do to follow this tutorial?
Hey there
I did some digging in the doc and experimenting and I figured out the following:
Vitis Unified IDE doesn't seem to automate the process as much as the old IDE did, I think mostly due to the wider variety of projects it can now handle, so the added granularity allows more flexibility.
Note I am using Vitis Unified Platform 2024.1 here
Refer to the diagram at 3:21 for the following:
- The System Project rectangle refers to the System project level, one of the two levels for which the new Vitis can be used to design. The other level is the component level, which refers to anything that can fit inside of this System Project rectangle/scope, including the Platform Project rectangle.
- an "Application project" in the old Vitis is nothing other than an "Application Component" in the new Vitis. However, as you may realize if you try to build one, it will not offer you to create a new "Platform Project". For this, you will need to create a new "Platform Component" seperately before creating the application component. It will also generate a new domain, as illustrated in the diagram.
Since in this tutorial we are not doing HLS Development, simply refer to the "System Development" box at the bottom of the Welcome Page in Vitis Unified IDE. Notice how the different components you need to create are already in order from top to bottom in this box!
You should go to the system configuration file (vitis-comp.json under your zynq_example_system on the lefthand side menu) to add your application component to your system project.
.prj files in the old IDE are equivalent to the .json files in the settings of your various components. It seems the new Vitis has moved away from the Eclipse engine and uses something very similar to VSCode....
BRAM Controller has AXI4 (full) Slave port,
is there anyway to do the "Burst Write/read" instead of writing/reading data one by one in for loop? for loop keeps the ARM busy
thanks!
Hi, I am following your playlist to learn about the PS PL integration, I have bram controller in the block design but it is not showing in the drivers in BSP. Can you help. I checked the xparameters.h file it isn't there as well.
How can i access the gpio within petalinux for example? I love your videos, keep it up❤
Hi, thank you!. it's very usefull video, but I have question, how does it work?! I did all steps based on video 1, but you didnt define UART IP, so you can't use hello world template
Can we program the PS using Python instead of C language.
If yes, can you please guide me through?
Hi, could you do a quick video about the differences between this version and the 2023.2 version with the new interface? There seems to be a lot of interface/syntax changes. I learned a lot from your zynq 1 video with 2023.2 but had to download 2023.1 to be able to continue with this video. Thanks for making this all make sense.
I'd recommend checking that you're using Vitis and not vitis HLS. Very different interfaces.
Can u confirm that XGpio_Initialize(&Gpio, XPAR_AXI_GPIO_0_DEVICE_ID); ==> need to set XPAR_AXI_GPIO_0_DEVICE_ID, not XPAR_AXI_GPIO_0_BASEADDR. Thanks for your great videos!!
Yeah I picked up on this too after the fact. In the next video (part 3) and github it should be fixed.
btw, can you confirm that in line 112 and line 119, the XBram_ReadReg(XPAR_BRAM_0_DEVICE_ID,i) is actually XBram_ReadReg(XPAR_BRAM_0_BASEADDR,i) thanks! cause it's writing to the base address of Bram