Vivado Tutorial: Turn Verilog IP into AXI Module

This video describes an overview of how I converted my Verilog IP into an AXI module in Vivado so I could test my design. I am currently testing with a PYNQ Z1 board so results may vary if you are working with a different board. If you have any questions, leave them in the comment section and I will try to answer them to the best of my abilities.

[@mriosrivas]

This is what I was looking for. Thank you so much, I really appreciate your effort!

[@kirtikumarbaba]

it's useful thanks.!

[@beccadls2838]

Didn’t understand a word of this but cool!

[@weiyizhang4317]

Hello, thank you for the lesson very much! I wonder is there any example which uses both input and output axi stream? Thanks a lot!

[@MonishaK-sh9bk]

i want to know how to give my data into the IP, using SDK , please provide any video or documents

[@iremnurcolak620]

Hello, what is IP? I was looking for AXI implementation but I came across IP in TH-cam a lot. I do not know what it is actually. Thanks :)

[@clintlemire8741]

Intellectual Property. In this context, it is referring to your design.