How to think about VHDL

Some general philosophizing about VHDL, what it was designed for, and how to learn it effectively.

[@kinanrabbat5769]

Banger video

[@engjds]

Been at this language for a while and I still pull my hair out on occasions, but lately its all been coming together since using component imports and generics, I tend to think of designs in terms of counters and glue logic, i.e. state machines, if you try and fall back on VHDL doing the power tasks without thinking in terms of hardware behind it, you will create some monstrously bulky designs, KISS method.
When you start, dont make the same mistake as I did, when you search for help, ALWAYS make sure the examples are SYNTHESIZABLE (can be programmed into hardware) or testbench which cannot, learn one first, not both at the same time or you might go mental!

[@b1tbanger]

The trick is to master structural modelling first. Once you have a good idea on how to structurally model the standard cells and megacells, you can later leverage the language's extensive libraries to model circuit behavior and leave the specifics of architectural implementation to the synthesis tool.

[@engjds]

@@b1tbanger thankyou for that tip, that is helpful!, I am at a point now where I can create mostly functioning designs, but clueless on test bench, if you know any good books let me know

[@b1tbanger]

@engjds I haven't found a book that covers that part of VHDL properly. I used VHDLwhiz's blogs to learn how to write them. The guy is a legend at this.

[@keenobaerry3195]

not in your class but going through the paces in CompE, thanks

[@samus4799]

Hi, i have experience with Ladder Logic. Do you think this would give me an advantage in learning VHDL?

[@engjds]

Nope, not unless you used it to siplify logic like using demorgans, karnaugh maps, state machine etc.

[@b213videoz]

Why must I even think about VHDL ? 🤪