How to Use a Procedure in VHDL
ฝัง
- เผยแพร่เมื่อ 30 เม.ย. 2018
- Learn how to use a procedure in VHDL to create cascade counters in a clock module.
The blog post for this video:
vhdlwhiz.com/using-procedure/
Procedures are a type of subprogram in VHDL that can be used instead of copy-pasting code. They are like mini-modules which can be invoked from a line of code within a clocked or concurrent process.
Unlike a function, which is the other type of subprogram in VHDL, a procedure doesn’t have a return value. Values can be returned from procedures through the parameter list though. The parameters can have any of the directions “in”, “out”, or “inout”, just like in a module can. The inputs may be signals, variable, or constants.
Another thing that separates procedures from modules is that procedures can contain wait-statements, while functions cannot. They can consume time. Because of this, procedures are often used in testbenches as bus-functional models (BFMs).
Procedures can be declared in the declarative region of the VHDL file, or the declarative region of a process, or they can be declared in a package.
*** Update:
The IncrementWrap procedure contains a bug that causes it to fail in newer versions of Questa/ModelSim that follow the VHDL standard more closely.
The Wrapped signal should be cleared outside of the If statement. See the updated version of the procedure in my blog post: vhdlwhiz.com/using-procedure/ - วิทยาศาสตร์และเทคโนโลยี
I've been a Verilog coder since the early 90's and I'm new to VHDL...but, this just blew me away! Very elegant and efficient, but will take some time and practice to get used to this style.
Great video, do not stop recording! I learn a lot from your channel!
Thanks, Piotr. More is coming. 😀
you are so organized, accurate, and explain simply! thank you very much!
Only one word ... Astonishing
Recommended procedure for performing laboratory work
1.develop a mathematical algorithm for solving the problem.
2.determine the required data types in the package.
3.study of differences in the design of functions and procedures in the VHDL language.
4.write the texts of functions and procedures.
5.write a test program.
6.Modeling and obtaining timelines. It is necessary to carry out testing of two functions and two procedures.
task1. function (procedure) of double representation of the population
presentation.
This is a function (procedure) of the bit_vector type → INTEGER. Late
(true) the rank of dual representation is assigned to the senior.
The number of bits of the vector is equal to 8.
task2. function (procedure) of preobrasovation of the first part of the presentation of the second part
presentation.
This is a function (procedure) of the integer type → BIT_VECTOR. First
the rank of dual representation is assigned to the senior. The number of bits of the vector is equal to 8.
THIS IS COMPLETELY MAGNIFICENT 😵😵
Chapeau and thank you a lot! :)
Thanks a lot. You are amazing
good to use "procedure"subprogram to reduce the code length,
For a software guys, this hurt watching. It's so hard to think sequence matters.
Sir, what is the purpose of Tick and why do you check clockfreqHz -1
I believe Tick is what manages the time passed. Every time Tick = ClockFrequency, one second has passed. This in turn control the hours, minutes, and seconds.
please help me
I had a slightly different Rev of the simulator. So I had to add Wrapped := false; in an else for the if Enable then in the procedure. It wasn't being cleared automatically.
Like so:
begin
if Enable then
if Counter = WrapValue - 1 then
Wrapped := true;
Counter
Actually, your new version of the simulator is correct. That was a bug in my code which I have corrected in the blog post: vhdlwhiz.com/using-procedure/
But I can't change the video.
Great work fixing it yourself!
Wow! This coding style is way too elegant for me 💔