FPGA Clock and timing concepts explained simply for beginners using two analogies!

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  • เผยแพร่เมื่อ 11 ต.ค. 2024

ความคิดเห็น • 13

  • @satpatel7508
    @satpatel7508 3 ปีที่แล้ว +8

    I generally percieve these things like my laundary, -- placing clothes, starting machine, drying the clothes and ironing. Fits well with the pipelining concepts too.

  • @AlejandroHernandez-xi4vl
    @AlejandroHernandez-xi4vl 3 ปีที่แล้ว +6

    I love your videos Stacey, thank you

  • @Leethal60
    @Leethal60 2 ปีที่แล้ว +2

    I'm glad you produced this video. I have an Counter AXIS IP to a FIFO to AXI DMA to ZYNQ PS on a Zedboard and couldn't meet timing until I slowed the F_CLK0 down to 80 MHz from 100MHz. I'm not sure which worker is having trouble putting on the lids though :)

  • @joelmandebi7212
    @joelmandebi7212 2 ปีที่แล้ว +2

    Great content Stacey. Thanks

  • @arinoba492
    @arinoba492 2 ปีที่แล้ว +2

    Came from reddit, seems like I will be here for a long time :D

  • @satpatel7508
    @satpatel7508 3 ปีที่แล้ว +2

    Great analogies! Enjoying your short and easy-to-understand videos!

  • @boyillahareeshreddy3410
    @boyillahareeshreddy3410 หลายเดือนก่อน

    Hi, I’ve been following your videos, and they are really good. I wanted to ask for a favor, if you don’t mind. Could you please make another video on STA with a real-time example, such as a FIFO or some protocols? In that video, it would be great if you could explain how to solve timing issues like negative slack, setup, and hold time violations.

  • @jogeshsingh854
    @jogeshsingh854 3 ปีที่แล้ว +2

    One analogy is that using synchronous clocking as far as possible and abstaining global reset In sequential circuits.

  • @eigenfield
    @eigenfield 8 หลายเดือนก่อน

    Before the next snapshot clock, where we are busy doing stuff to get ready (and make sure that our hands are not in the way), is there another clock used here aside from the main snapshot clock?

  • @shams350z
    @shams350z 2 ปีที่แล้ว

    are those galaxy buds ?