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afrikaans is my favorite accent

The block design or Altera's Platform Designer are very impressive tools to design. However, knowing that a microblaze/nios connects to an interrupt controller for example is what I still don't understand. Do you need to take a course/learn about computer architecture to understand all those blocks or do the vendors provide them. I feel like if you told me to design LED toggling, I wouldn't know which blocks to connect or how to connect them even though I know where to click on the software to access them. How would I go about that?

You should consider teaching as a job.

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Thank you

Hi Stacy, I just discovered your channel. I was wondering if you have an example streaming UDP data to a remote host. I'm trying to receive the stream with a python socket, and account of dropped packets (where I'm using a Zynq to transfer the data). Thank you so much!

For XBram_WriteReg as well as for ReadReg, why you have used device_id instead of base_address, please answer as i am going crazy abt it

Is there a video showing how to use a pmod pin as an external clock? Sometimes I think I works for some pins and not for others and I dont completely understand why

THIS WAS ONE YEAR AGO ... WHAT ABOUT NOW ?

Thank you for useful video !! ^^

When you hit Run and Launch, where actually is the program running?

Can you share basic videos of explaining the inter clock and intra clock issue

Finally, a tutoral on Xilinix SoC's that makes sense.

Don't know if it is easy to do but can you make videos with higher resolution? I mean it's a bit hard to read the code in 720p. Overall it's a nice lecture, good job!

I absolutely love how involved you are throughout. Amazing.

great

Nice video

Hands up everyone who has a favorite state machine! 👍

Interesting video, the idea of axi was alien to me until yesterday when I binged your videos. I understand it more and it makes a lot more sense for how more complex FPGA designs can exist. A question I do have though, when it comes to design architecture. If we look at your microphone to udp example. If you wanted to have a programmable gain or frequency response, or anything about the design to be programmable, how would you incorporate that? My thought would be you could use registers in a memory block to hold configuration data and through the axi stream set those registers over udp. Then your microphone or other elements can read those configuration registers. Is this how it would be done or am I completely off?

Really nice vid, was just struggling with this. Would be interested to learn about pipelining an axi stream without breaking the backpressure

Hi stacy, would you be inclined to do private lessons via zoom call?

It's really helpful for beginner like me. Have you implement that neural network on fpga. Thanks

Thank you very much for your materials! ❤

*Summary* * *(**0:00**)* *Purpose:* The video explains an AXI-Stream Arbiter example designed to debug data streams. It combines multiple AXI-Stream inputs and outputs them to a single UART interface for monitoring. * *(**2:38**)* *Key Components:* * *AXI-Stream Snoop Ports:* Non-intrusive interfaces that allow observation of data on the AXI-Stream bus without affecting data flow. * *FIFOs (First-In, First-Out):* Buffers used to store incoming data packets from each of the four input AXI-Stream interfaces. * *Arbiter:* Logic that manages the selection and prioritization of data from the different FIFOs to send to the UART output. * *State Machine:* Controls the overall operation of the arbiter, with states like IDLE and WRITING, ensuring data is transmitted in complete packets. * *(**2:38**)* *Arbiter Logic:* The arbiter employs a priority scheme to choose which FIFO's data to send out first. In this example, FIFO 0 has the highest priority and FIFO 3 has the lowest. * *(**2:38**)* *Data Flow:* Data comes in through four AXI-Stream Snoop Ports, is stored in individual FIFOs, then the arbiter selects which FIFO to read from based on priority and data availability, finally outputting that data to a UART for debugging. * *(**6:11**)* *Important Concepts:* The video emphasizes understanding: * *AXI-Stream Handshaking:* The use of 'ready' and 'valid' signals for data transfer. * *Synchronous and Asynchronous Logic:* Different types of logic and their importance in FPGA design, especially for state machines. * *Packet Integrity:* Ensuring complete data packets are transferred without interruption. Summarized by AI model: gemini-1.5-pro-exp-0801 Cost (if I didn't use the free tier): $0.0675 Input tokens: 16454 Output tokens: 941

Loved this video stacey! Your way of looking at systemverilog and why we use certain constructs in certain way, is amazing, easy to understand and remember too. Thanks a ton....😇

Lovely video! you're the best when it comes to FPGAs! Can you make a video about Dynamic Function Exchange (Partial Reconfiguration) please?

Hello Stacey, Hello FPGA devs, i have a GOWIN Tang Nano 1K , on board it is equipped with crystal oscillator that outputs 27MHz as clock frequency. my question is: is that 27 MHz is "exactly" 27000000 Hz ?, or it's something closer if you know what i mean ,,,,,, i dont have an oscilloscope to test the purity of that 27MHz

Hi, www.youtube.com/@FPGAsforBeginners, In the advance level of out assignment, I think there should be some correction, If we follow the above examples. According to me it should be written as "assign out[(NUM_BYTE-i +1)*BYTE_SIZE-1 -:BYTE_SIZE] = in[(i*BYTE_SIZE)-1 -: BYTE_SIZE]". Please correct me if I am wrong! It might be correct If we ignore the previous examples :)

I have some problems. Can I use this design with Vivado 2018.2 Stacey ?

I didn't know about this new series ! As an embedded engineer (not fpga, more MCU, MPU) they get me a feel for the field! Thanks Stacey

Nice work Stacey!

Wow, this is super helpful, you really simplified it down, thanks!

Hello ma'am, the website is not responding ...... please help!!

You connect your peripherals to the interconnect_aresetn, when the Processor System Reset has a dedicated output called peripheral_aresetn. Is this going to be a problem? The instinct tells us that there are differences between these two resets generated by the reset IP. What can you tell us about that? Thanks!

Thanks Stacey!

good

thanks to start posting video after long time

Hi Stacey what sort of throughput could you get? I am thinking of using ethernet RMII between an FPGA and a SOC without using a PHY.

Great Job Stacey...

Great job, Stacey. You do it very well. It pleases me that women also choose to geek out in these fields. I wish you all the best.

yeay ! )

Great Stacey! Stacey I just wanna ask: I currently code in VHDL as I find it very intuitive and engaging. I see you use verilog and system verilog most of the time. Is verilog (system verilog) easier to use in HDL design than VHDL or what is your reason for your choice of HDL? Thanks.

It awsome that you’re helping so much to open source FPGA design. I remember when I first started designing circuit boards and having great tools and recourses to learn from. Your videos are gonna be my goto now that I’m trying learn about FPGAs 😁

Top news! Well done!

Really nice, thank you very much

As usual, very useful video. Thank you. is there any chance that you can use one ETH IP with Zynq? and show us the source code for the ETH configuration. Also, PCIe is very common these days. you could use it with ZYNQ as well. Thank you so much for your videos

Am a PCB layout / PLM database guy by day and a Verilog noob by night. Have been playing with Verilog over the past few weeks on my Spartan3A Digilent board and have now managed to interface a WD65C816 (memories of C64 asm!). There's now a UART'ish thing with Tx & Rx and I'm just about to finish implementing Steve Wozniak's WozMon. So glad the YT algorithm suggested you as now I can see how it should be done. Looking forward to studying your series.

loved the video, thank you very much 😊

Bedankt

Absolutely great explanation👏👏