Another great video. I can read from your face how eager you to teach great stuff to the people. Can you make another video about what should an FPGA design engineer know other than HDLs? We are seeing Phyton, C/C++ as scripting languages, DSP etc in job qualifications. For example DSP, are they expecting DSP knowledge from you or embedding DSP processor to FPGA? I want to know how you guys combine all of these and for what?
I would say generally Python/Matlab for algorithm development, and python/c++ for driver and host-side code is useful. But otherwise it depends also on the company, the industry, and the FPGA application. A junior or new grad can't be expected to know everything, but after time in a specific industry you do pick up side skills that are relevant. Eg: after time in RF you will pick up DSP skills, and probably c++. And in high-frequency-trading you'll pick up other skills too. So you can't say you need DSP skills for sure, or anything else. it just depends on the application. Also some companies have whole departments who develop the algorithms, and the FPGA developers just convert them to the FPGA. So a general understanding of math and use of Matlab/Python/eg will be helpful.
Hi Stacey, great video! I have Vivado 2021.2 version and it gets stuck at 'Customize IP' on trying to add a simple FIFO. Is there some known issue with this version of Vivado?
Do you have any sources of code for Interrupts to PS (Zynq or MicroBlaze) from the PL. I have tried to following the examples for Interrupt enabled GPIO (Xilinx provides example code but I have not gotten it to work on A9 processor). My Goal is to acquire data from VHDL code running on PL fabric, then interrupt the processor, that will then read the data from a bank or 16 32-bit registers and send over lwIP to an application listening to a given port. I will have to go to a polled mode if I can't figure this out soon - the most inelegant solution of all. I have already tried to use an AXI Stream FIFO and DMA, but came up short there as well. Thanks for any leads or pointers you may offer. Keep up the great postings. (I could not find my comment from a week ago also saying that I learned some tips about the easing the Vivado anti-friendly behavior towards VCS.) Knowledge is powerful, keep it up.
Thanks so much! Did not know about these Vivado tips in regards to version control. Thanks!!!
Waiting for the video on AXI!
Another great video.
I can read from your face how eager you to teach great stuff to the people.
Can you make another video about what should an FPGA design engineer know other than HDLs? We are seeing Phyton, C/C++ as scripting languages, DSP etc in job qualifications. For example DSP, are they expecting DSP knowledge from you or embedding DSP processor to FPGA? I want to know how you guys combine all of these and for what?
I would say generally Python/Matlab for algorithm development, and python/c++ for driver and host-side code is useful. But otherwise it depends also on the company, the industry, and the FPGA application. A junior or new grad can't be expected to know everything, but after time in a specific industry you do pick up side skills that are relevant. Eg: after time in RF you will pick up DSP skills, and probably c++. And in high-frequency-trading you'll pick up other skills too. So you can't say you need DSP skills for sure, or anything else. it just depends on the application. Also some companies have whole departments who develop the algorithms, and the FPGA developers just convert them to the FPGA. So a general understanding of math and use of Matlab/Python/eg will be helpful.
Very insightful thank you so much
it a great video and very good clarification ,thank you.
Thank you that was really helpfull, But is it the same process when generating ip s with lattice FPGAs ??
your videos is so cool. make it more!
Hi Stacey, great video! I have Vivado 2021.2 version and it gets stuck at 'Customize IP' on trying to add a simple FIFO. Is there some known issue with this version of Vivado?
Stacey do you think you could someday make tutorials on using arm cortex M1 that's available for free for arty a7 ?
Yup I will do! Will add it to my list
Hey Stacy, questio: using Ip block (which is lets say encoded) in the final product, will i have to pay for it? for each block? thanks
Do you have any sources of code for Interrupts to PS (Zynq or MicroBlaze) from the PL. I have tried to following the examples for Interrupt enabled GPIO (Xilinx provides example code but I have not gotten it to work on A9 processor). My Goal is to acquire data from VHDL code running on PL fabric, then interrupt the processor, that will then read the data from a bank or 16 32-bit registers and send over lwIP to an application listening to a given port. I will have to go to a polled mode if I can't figure this out soon - the most inelegant solution of all. I have already tried to use an AXI Stream FIFO and DMA, but came up short there as well. Thanks for any leads or pointers you may offer. Keep up the great postings. (I could not find my comment from a week ago also saying that I learned some tips about the easing the Vivado anti-friendly behavior towards VCS.) Knowledge is powerful, keep it up.