05:50 - Min period = Tsetup + Tcomb(prop delay) + Tcq (clock-to-q delay) Thold has nothing to do with min period. Hold time violations occur when Tcq < Thold
i dont mean to be offtopic but does anyone know of a trick to log back into an Instagram account? I was dumb lost the account password. I love any help you can offer me!
The best reference for digital timing is Sarah and David Harris' book "Digital Design and Computer Architecture" published by MK. The concept was clearly well explained in the book. The authors summarized and presented the subject very well.
Great video. I recognise those diagrams from the Art of Hardware Architecture book, but listening to you explain it all made it much clearer. I'm fairly new to FPGA design, so timing stuff is still somewhat of a dark art for me.
From what I understand, the reason you need to pay attention to it, is that unlike the graph shows, when the bit goes from 0 to 1 or from 1 to 0, it doesn't happen in 0 time, it take a few mili/nano seconds. That's why we need to wait for the change to happen, so we won't accidentally capture the signal when it's between the 0 and the 1 signal.
I love timing errors... when I started to work (still in dummy mode, not productional) I never paid attention to them sometimes the design worked sometimes it failed (and with sometimes I mean: sometimes the synthesis output worked, but another time the synthesis output failed on the FPGA). It only permanently worked once the timing errors were solved
How is that your equation shows Tclk (min) = (Tsu + Thold + Tpd) ? Why is even hold part of the frequency calculation for full cycle path ??? I do understand only if Tpd < Thold only then Tclk (min) = Tsu + Thold.
Nice video. In your cascaded flip flop example, is there ever the case where the first flip flop is too fast, and the data gets to the second one during its setup time?
Asynchronous counter is sequential circuit, but it's not synchronous. Its name is self explanatory. Youll call a circuit synchronous sequence only when all of them are driven by a single clock. Hope I cleared your doubt
This is an engineer I would be proud to work with. The world needs more people like you!
05:50 - Min period = Tsetup + Tcomb(prop delay) + Tcq (clock-to-q delay)
Thold has nothing to do with min period.
Hold time violations occur when Tcq < Thold
Great video. Looking forward to timing constraints on input/output delay ...when dealing with chips outside the FPGA. Always get confused by it.
Thank you. Your videos are so educational. We learn so much from them.
i dont mean to be offtopic but does anyone know of a trick to log back into an Instagram account?
I was dumb lost the account password. I love any help you can offer me!
thats very helpful video . I am following all your videos .tnx Russel.... - from INDIA
The best reference for digital timing is Sarah and David Harris' book "Digital Design and Computer Architecture" published by MK. The concept was clearly well explained in the book. The authors summarized and presented the subject very well.
At 7:00 , you show tclk(min) as function of hold time. Is it correct? Maxm frequency, I think, do not depend on hold time.
Great video. I recognise those diagrams from the Art of Hardware Architecture book, but listening to you explain it all made it much clearer. I'm fairly new to FPGA design, so timing stuff is still somewhat of a dark art for me.
What's that book? I didn't see it on Amazon.
great videos, always simple and clear.....hi from MotherRussia :)
short, sweet, and crystal clear. and in English too :). would have been nice to have an explanation of why setup and hold times are necessary.
From what I understand, the reason you need to pay attention to it, is that unlike the graph shows, when the bit goes from 0 to 1 or from 1 to 0, it doesn't happen in 0 time, it take a few mili/nano seconds. That's why we need to wait for the change to happen, so we won't accidentally capture the signal when it's between the 0 and the 1 signal.
Please do a video about how to fix timing errors (including setting timing constraints).
Your explanation is simple and awesome !
I love timing errors... when I started to work (still in dummy mode, not productional) I never paid attention to them sometimes the design worked sometimes it failed (and with sometimes I mean: sometimes the synthesis output worked, but another time the synthesis output failed on the FPGA). It only permanently worked once the timing errors were solved
That propagation delay from the time of clock formula is from flipflop1 or flipflop2?
Man you are awesome. I wish I was as intelligent as you are😂
How is that your equation shows Tclk (min) = (Tsu + Thold + Tpd) ? Why is even hold part of the frequency calculation for full cycle path ??? I do understand only if Tpd < Thold only then Tclk (min) = Tsu + Thold.
if its just wires - it doesnt matter right? its only when its a register on feedback or output to a pin it matters. (clock synch)
and one more question - why doesnt pipelining get as in the terrahertz - propagation delay wise, it could be 1 micrometre between registers!!!!
Thank you, it's so clear.
Amazing, thank you very much! Cant wait for more vids.
Good job!
Very well explained!!
Help me a lot thank you!
Really great video. Thanks!
great explanations dude! thanks!!
Nice video. In your cascaded flip flop example, is there ever the case where the first flip flop is too fast, and the data gets to the second one during its setup time?
100 megahertz is 10 FEET. as if it would be that much inside one side to the other, i reckon. have u got experience with this EXACTLY?
r u ok with matlab sinulink use in fpga?
@nandland are you planning to refresh Go board in near future? Thank you for the videos!
No
very nice video .... can you write a post on "removing glitches using gray code "
1 ns=20 cm, actually most of the delay is due to capacitance, not the travel length of the wire.
is Asynchronous counter.....Synchronous sequential circuit???
No one ever answered me this question.......
Asynchronous counter is sequential circuit, but it's not synchronous. Its name is self explanatory. Youll call a circuit synchronous sequence only when all of them are driven by a single clock.
Hope I cleared your doubt
Perfect
Well can u please create a vhdl tutorial playlist
Parabéns amigo continue assim abraços
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ily
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