80% of the questions we covered in the last month and a half (sophomore year) in EE! Thanks for giving us the insight on what to look for and to keep on the tip of the tongue
Using this to study for an RTL design internship interview in 2 days. Ever since I started watching your videos 5 months ago, I've fallen in love with FPGA design. Thanks for all you have done for me!
I think that SRAM is faster than DRAM, and both flip flop and latch can have clock, the difference between them is that the output flip flop happens when the clock is going up or going down, meaning in the transition from up to down or from down to up ( 0 to 1 or 1 to 0 ) however in latch the output happens when the clock is up or down depending on the design of the latch
This is really nice. Good questions and I learned new things today. But At 7:50. Are you sure DRAM is faster than SRAM ? 1. SRAM uses multiple CMOS transistors to store a bit(typically 6-8 CMOS FET's) while DRAM is made up uses single transistor plus a capacitor. So memory cell of SRAM occupies more area than memory cell of DRAM. DRAM is thus more dense and can fit more memory bits in same areas as SRAM cell. 2. However, DRAM needs to periodically refresh (hence dynamic and not continuous power supply) the charge on the capacitors of its memory cell which tends to leak with time while SRAM cells remember their logic due to cross-coupling(feedback) and continuous power supply from VDD/VSS power rails (which makes it power hungry). 3. Data can be read from SRAM at lower latency (order or more) and higher bandwidth (several orders) compared to DRAM. So SRAMs are faster than DRAM. 4. SRAM is used for very small (KB to few MB) fast on-chip L1/L2/L3 instruction and data caches on cpu's/gpus or or scratch pad memory in embedded socs while DRAM (GBs to TB) is used off chip to store high amounts of data. 5. SRAM per bit is more expensive in terms of area, power, and money compared to DRAM so SRAM is only used in small sizes (on chip or off chip) and to store data whose access time is critical to speed.DRAM us used when higher capacity is needed but speed of access is not important.
it is nice bro, in architecture system, SRAM is also called "Cache". And Cache is quickest memory in architecture system. It used to optimize the execution time of processor. Then, it is the best way to make processor runs faster.
@@duymanhnguyen8302 generally, you're correct, but you're confusing function and implementation. Cache is a type of memory (function), while SRAM is a technology (implementation). You could just as well implement a cache using DRAM or some other memory technology. The speed also depends on the size of the memory of course!
Appreciate the video. I had an interview for digital design (with spacex) even though I'm a computer engineer. The questions that got me are the following: how do do know cdc data is ready when using dpram? explain some timing constraint experience how familiar are you with making build scripts (in vivado, libero, quartus, etc.) explain a fpga design you have been the lead of (schematic, worst case analysis, timing analysis, embedded c, etc.) just wanted to give you an idea of what I see in the modern workspace. I always send co-ops to your videos. keep up the good work!
It was specifically for a firmware engineer position. At my job there are a good mix of people that are senior level digital design engineers that can do engineer 1/engineer 2 level skill set C programming work and vice versa for software engineers doing VHDL. VHDL modules like discrete io control, SPI, I2C, etc. may be given to a software engineer like me who knows VHDL from school if staffing resource constraints are an issue. It's usually the timing closure, top level architecture design, etc. that would be out of the SW engineer's skill set.
@@kdjohnson321 I'm also a CE graduate interviewing for RTL/Digital Design, so it's not that strange! I also think basic programming skills should be expected even if your job is to design hardware
I graduated recently and decided I wanted to work with fpgas after some experience with them during an internship, just after applying for a graduate role I watched this video and used your site to prepare for the interview and I'm happy to say it paid off and I got the job! Thank you very much for helping me achieve my goal of becoming an fpga engineer
@@akeemlouigarde4946 sorry for replying 10 months after the fact 😅 I'm still with the company and I've had a promotion, it's been an extremely satisfying job and I can easily see myself working with fpgas for the rest of my career
I was always taught that the difference between Moore and Mealy was not about what state to go to next but more about the outputs at each state. In Mealy, the outputs are dependent on the current state and the inputs, but in Moore the outputs are only dependent on the current state only.
And "Mealy" is not spelled "melee". This erroneous answer seems to have caught out candidates I have interviewed, so Nandland really need to get this changed. Start with the answer the Nandland web page as its easier to fix text. But please get "model answers" right!
The way I have remembered Mealy and Moore machines is that the Mealy machine will typically require less states to implement. The input and output are shown next to each other during the transitioning state. Because the output depends on input and present state, the output will see perturbations from the input. This means we must register the output into another DFF to stabilize that output. The introduction of another DFF will cause a 1-cycle delay, but you will at least be stable. The Moore machine, if I am not mistaken, will have "moore" states typically, but its output will always be stable because its output is only dependent on its current/present state. I hope this helps!
"Pretend like you're interviewing with me for your job, pause the video, give your answer to me. I'm not going to hear it obviously, we're not there yet with the internet but.. maybe some day". Haha, looks like we're at that day
These videos (and also your site) are extremely helpful. Just had several RTL design interviews the past week and they asked similar questions, so thanks so much man!
@@TF-km2ls Lol they were doing everything in high level synthesis and the questions revolving HLS and hardware abstraction caught me off guard. so it didnt go well. I dont blame this video tho, its my fault for putting all my eggs into RTL concepts
Thank you for your great video! we have different job positions regarding FPGAs like: RTL designer, FPGA specialist, Embedded DSP designer. Each one can have different questions ❣
I believe that Sram are much faster than SDRAM, nad main difference is that Dram is much more volatile than Sram so we need to refresh periodically but in sram its automatically refreshed as there is crossed couple inverters pull the data continuously with out recharging , and can also diffrentiated by the construction of these memory
"It depends." For large sequential memory reads/writes, DRAM is faster. SRAM is faster for non-sequential "random" reads and writes. So it depends on the application.
SRAM are usually smaller compared to DRAM, but SRAM can give the word in several nanoseconds and it is easy to use with FPGA, because SRAM is very similar to FPGA’s BRAM. As for DRAM, remember timing settings in BIOS for memory modules? That is quite complicated to implement in FPGA, but possible. Some FPGAs have hardware DDR SDRAM controller for this case.
Also, nowadays there are PSRAM chips, which are pseudo-SRAM. Internally they based on DRAM, but have SRAM-like interface, combining ease of use and big size.
I knew most of the answers to these, but I always flop on interviews because I get tripped up on terminology. This video has been extremely helpful in giving concise answers for an interview format. Thank you!
Thank you a great introduction to FPGA I have a lot of discrete logic family experience mostly the 74 ABC families and some 4000 series (I got as far as treating them as analogue parts). I was surprised that I actually new the answers plus more detailed knowledge about how the digital blocks worked and what they are used for.
Mixed up things a little while talking about mealy and moore state machines. It's the output which depend either on the state and the input (Mealy) or only on the state (Moore). You were talking about state transitions, which depend on both variants on state and input. Maybe add a comment to the video to not confuse some newbies watching :-) Besides, great video! :-) Liked it.
Synthesis tool - can be provided by an Independent CAD tool Vendor Such as Synopsys or Cadence. Commonly FPGA vendors can provide two options a). Their own tool like LSE for Lattice and b. third party tool e.g. Synopsys Synplicity. Occasionally a student can try to switch between two Synthesis tools in the same FPGA setup. But Xilinx Vivado will use its default tool and this is most recommended. when you switch tools sometimes you need to provide a different timing file - TCL script. Running an RTL code in two tools is not necessarily the smartest thing to do.
I have been writing Verilog Code since at least 1994. I finished my MSEE in 1990. I have now been coding Verilog and Matlab for almost 30 years. Its very good that you made this Video. Good questions too. I wish you add more content - one common area would be 1. Clock domain crossings - in Verilog. 2. FIFO design with Grey coded counters in Verilog - Cliff Cummings - 1994 3. AXI-4 streaming Interface - which requires 4 signals. 4. AXI-4 Slave design.
So the flow in an FPGA is Synthesis-> Map and Place and Route. The Netlist at the time of mapping does not have the RC Interconnect information. But its very useful in terms of the DSP resources and LUT count and DFF usage and Block RAM usage. This is why doing a three part synthesis flow provides one information in a "timed " way compared to all in flow Synthesis flow. I commonly check the Map resources Table to see if the RTL is really using too many DSP resources and BRAM.
Bus arbitration and methods of arbiter operation might be an area where you wanna add questions. Such as what is the difference between round robin arbitration and priority coded arbitrations.
I think the questions are reasonable, some answers are fine, but not all. Some answers are wrong enough to give you a bad outcome in an interview. Here are some corrections: q3: diff flop latch A better answer is the difference has to do with how the output gets updated. When a latch is open it is 'transparent.' Changes on the input D show up on the output Q (after some tprop). In a flop the output does not change until the flop is clocked. So changes on the input before the clock are not visible on Q. When a latch closes D will no longer effect Q, until the latch opens again. q4 choose an fpga FPGA's are _always_ slower and bigger than an equivalent std. cell design. It is fundamental to how FPGAs provide the re-programmable feature. E.g. a 14nm FPGA will achieve ~+500MHz in logic/processors, a 14nm std. cell design will achieve ~++2GHz, all other things being equal. This is because FPGAs implement some logic indirectly (luts, muxes, etc.) while std. cell designs implement logic directly (nand, nor, etc). This speed difference is the reason FPGAs have to provide hardened DSP blocks and the like to mitigate the performance degradation. The main points are: ASIC/std cell's are costly to manufacture, can not be changed without re-manufacture while FPGAs have a better cost model, can be iteratively designed and can be modified even in the field. i/o has nothing to do with fpga vs std. cell. high mem b/w requirements have nothing to do with fpga vs std cell tons of math operations, these are always as fast or faster, smaller, less power in a std cell design all the applications you mention are easier to implement in a std cell design than FPGA. q6 diff between sram dram You should skip this answer completely and go find your own. If you gave me this answer it tells me the candidate does not understand the difference. There is a difference between access time and bandwidth. DRAM is not faster than SRAM, do you see any cache tags or TLB's built from DRAM? Nope, all SRAM. All things being equal SRAM has more available bandwidth than DRAM due to refresh overhead and due to the row activation, column activation semantic required by the multiplexed address pins of DRAM. DRAM bit cells are fundamentally smaller (3 or 4T cells) than an SRAM bit cell (6 or 7T cells). That is why you need to refresh DRAM, it's charge will degrade, not SRAM. 3/4T makes DRAM great for bulk RAM. q9 what is meta-stability Again, good question but go find another source for the answer, using this answer will not help you. Anytime you violate the setup and or hold time of a flip flop you risk putting the flop output into a meta-stable state, i.e. it is not reliably a logic 0 or a logic 1. The flop's physical design determines how long it takes for the flop to stabilize. The signal source, internal or external, has nothing to do with the likelihood of inducing meta-stability. If the signal is asynchronous to the clock used by your flop there is a probability of inducing meta-stability. The risk of meta-stability is statistical, the more asynchronous the driving clock to the capture clock the more the risk of meta-stability. This is the reason dual flops are used to capture source asynchronous signals, including those crossing a clock domain. The dual flops reduce the probability of a meta-stable event to near infinitesimal. q16 clock crossing Fast vs slow is not the issue. Two clocks of the same frequency but not synchronously related still require meta-stable filtering techniques. q18 melee(sic) vs moore This is text book stuff, good question for junior people, if you are one you should have this exactly memorized: Mealy: outputs determined by current state and current inputs. Moore: outputs determined only by current state
I WISH YOU HAD A CHANNEL TEACHING FPGA FOR BEGINNERS. YOU ARE REALLY GOOD AT TEACHING. YOU CAN HAVE A CLASS ON TEACHING EVERYTHING ON FPGA'S . Like what is a FPGA ,real life examples of why a person would use one , what are all the pins for ,,how to program them and basic manufacture design of FPGA. I personally would be on that channel every single video...no one has that ...i have been checking for a while now. you are good are teaching
My background isn't electronics, so this is a very useful guide for highlighting my knowledge gaps. One question I have - is the assertion that DRAM is 'larger and faster' than SRAM correct? I always thought that SRAM was faster, due to the lack of need for refresh cycles which delay read/write, and use of directly driven flip flops, rather than gate capacitance to store the bits, hence it's use in cpu cache. As a software engineer, I find the whole topic of being able to design hardware at the HDL level of abstraction fascinating. It's high enough level to not require lots of phsical knowlege, yet low enough level to understand how it maps to real hardware (or rather how it could be mapped to real hardware, outside a clever device like an fpga).
"It depends." For large sequential memory reads/writes, DRAM is faster. SRAM is faster for non-sequential "random" reads and writes. So it depends on the application.
That is a great speech and very helpful for my next interview. But at 8:14 you said that DRAM was much faster than SRAM ? I think that is SRAM faster than DRAM ? Is it right ?
Hey buddy, it's a Fantastic video, but I think you made an error somewhere. at 8:03, you said, "DRAM is larger..." If you are talking about a single DRAM cell vs a single SRAM cell, then the SRAM cell is much larger than the DRAM cell.
DRAM is not faster than SRAM because DRAM requires constant refresh to retain data and CPU cannot retrieve data from DRAM while it is being refreshed. In contrast, SRAM, since it's static, it can be accessed anytime without waiting. And because of the smaller size of SRAM, walking through the cache pages is much faster than the bigger DRAM.
I recently landed a job as an FPGA engineer. They asked pretty much the basics. However, I wasn't able to answer a couple of them. Could you help me with that? 1. Using IPs(microblaze), HDL wrapping and writing C programs using the Xilinx SDK vs Doing everything using VHDL from scratch to finish - Which method is more efficient in terms of timing, area, and resources? 2. Simulation looks good, synthesis and implementation look good, a bitstream is generated and FPGA is programmed. However, the FPGA doesn't function as per requirements. How do you go about debugging starting with your bitstream? I think these two questions are critical.
1) Writing VHDL will likely be more efficient, but more time consuming. 2) I'd look for ways in which my simulation was deficient. How good is my test coverage? Are there situation I haven't covered? Does my simulation correctly represent my clocks? How well have I simulated my resets occurring? I'd try and infer possible issues from the precise way in which my design doesn't function, can I figure it out by looking through my code? Failing that I'd debug my design live on a device by adding debug in various forms, counters, capture streams etc, and hope my build time isn't too terrible.
i think you made a mistake on the sram dram part. i thought sram is faster than dram because sram uses transistors primarily for storage rather than the capacitive storage that dram uses, which takes time to charge and discharge.
Your answer to the difference between Latch and Flip-flop, Another more prominent interpretation is the Latch is level triggered and Flip-Flop is edge triggered.
"Getting rid of metastability" - to be exactly: never, but you can reduce the probability to extremely unprobable (probability reduces by a factor by each FF stage), see also MTBF. Or to never cross clock domains of asynchronous clocks🙃
SRAM is faster,and the difference between f/f and latches we can say they both use clock but in case of latch it works as enable or disable and in case of f/f it is triggered.Correct me if I am wrong thank you
A latch doesn't need to be clocked in the sense of synchronicity, e.g. an SR latch has two stable states which can be selected simply by "clocking" either of its inputs.
I think there is a mistake on the question about moore and mealy FSM. I think the the main difference is the whether the output depends on the input or not, not next state.
Yes, multiply accumulate or MAC instructions are how DSP filters like an FIR filter are executed efficiently in hardware. Essentially you are multiplying the filter coefficients with the samples and accumulating the results likely using a circular buffer
I thought synchronous meant that was timed with the rise or drop of the clock and a synchronous could have a clock from an external signal but was not in line with the timing...
I've heard both. I think saying Async is "not aligned with any clock" is more accurate. I find for beginners it's easier and more understandable to say sync = clock, async = no clock. But yeah maybe I should be a bit more careful here.
Appreciate your help! I really needed something like this. But now I have couple of questions for you, 1- What companies, from your experience, can be good examples of a working environment in this field? 2- What do you exactly do in such a job? In boring details please..
1. Every company is different. Hard to generalize. But being an Engineer in general means that you have a lot of responsibility and control over your job. 2. You code! Lots of RTL and Testbench writing mainly. Working in the lab sometimes, design reviews with other disciplines, etc. It's fun!
I have a little bit confused in Q22. What is a DSP tile in FPGA? Can you give me a simple way to understand that? ^^ I hope I will get as soon as answer from you ^^
Even though these questions seem relevant, they are really like a university course exam. I'd never hire a candidate based on answers (on pretty simple) random questions. A minimum requirement today is a coding interview (and not just a typical FIR filter BS), and an actually good interview is of a problem-solving type. So giving a candidate a real life problem to think of possible implementation, to sketch a microarchitecture and to write some code example. Or find a problem in an existing design code example.
@@sj9184 Yes and no, I also wouldn't structure an interview with an intern in that way either. First, some of the questions are too basic for an electrical engineering student, some are not too relevant (you don't need to know what BRAMs, DSPs or PLLs are, you can learn that). Ofc some would make sense, but an intern should still be able to demonstrate basic coding skills (no necessarily in VHDL/Verilog), ability to think algorithmically, ability to do some basic problem-solving, ability to read documentation, etc.
I think you missed a very basic differences between SRAM and DRAM - DRMA need refresh, SRAM does not. This is significant because refreshing DRAM will tie up more clock cycles and FPGA complexity.
About as long as I did would be fine. A few sentences to show that you know what the interviewer is asking. You can always ask the interviewer if they want you to go into more detail. It's a conversation!
Granted I'm an EE student and likely won't be working with FPGA's when I graduate but these questions were a lot simpler than I expected, and I didn't like my FPGA course :P
You'll notice when you get to the industry, a lot of the interviewers are older guys who don't have a solid grasp of what FPGA's really are. They're either in too much of an administrative job to care about learning, or they're close enough to retirement so they don't really have to learn it. Either way, you're the next generation of knowledge. Having a basic understanding and being able to talk about digital design is what they want to hear.
Your video are so good and helpful. I appreciate that you made it! I have a question. I studied electronic engineering in university and got my masters degree in Korea but when I graduated I got a job as a software engineer and worked for 1 year. I moved to the US and I realized I want to start over my career as a FPGA engineer or anything related about that position. What do you recommand for me to study? Or for interview. It's been a long time i haven't studied about digital so I think I should start over all basic major knowledge and a small project by myself. Actually, I have no idea how to start a project in FPGA field if you can recommand it as well it will help me too. I have no experience any studying or interview in US. I will really appreciate your advice.
One other really important thing you should have mentioned is . There are three major classes of timing paths on an FPGA. a. Paths which start at a CLK pin of a flip flop and go CLK-> Q + Logic Delay and terminate on the D input of the destination DFF. b. Timing paths which start at a Primary input and end at a D input of the first DFF it encounters - PAD delay included. c. Timing paths which start at the CLK pin of a final DFF and end in a primary output. All Static timing analysis works with these three classes of timing paths. The difference between and ASIC STA and FPGA STA is the following the ASIC STA is run at slowest process, maximum and minimum VDD and maximum and minimum operating Temp. For a proper FPGA timing analysis one must run it almost like a ASIC STA. The .sdc file is common between Synthesis and STA tool.
Almost nothing was said about ASYNCHRONOUS LOGIC. The very first example is combinational logic, the latches mentioned are asynchronous as well. Of course, asynchronous logic should be avoided, because synthesis tools work better with synchronous logic (RTL=Register-Transfer-Level), and asynchronous logic can provide bugs, metastability and cancer (just joking).
Thanks Doug Demuro of Embedded Systems
😂
Lol so true , great video BTW
Thats the same thing I though when I watched this
Very true
omggggg
They literally asked questions straight from here and I got the internship position. Thank you so much!
Congrats!
80% of the questions we covered in the last month and a half (sophomore year) in EE! Thanks for giving us the insight on what to look for and to keep on the tip of the tongue
Using this to study for an RTL design internship interview in 2 days. Ever since I started watching your videos 5 months ago, I've fallen in love with FPGA design. Thanks for all you have done for me!
I think that
SRAM is faster than DRAM, and both flip flop and latch can have clock, the difference between them is that the output flip flop happens when the clock is going up or going down, meaning in the transition from up to down or from down to up ( 0 to 1 or 1 to 0 ) however in latch the output happens when the clock is up or down depending on the design of the latch
This is really nice. Good questions and I learned new things today.
But At 7:50. Are you sure DRAM is faster than SRAM ?
1. SRAM uses multiple CMOS transistors to store a bit(typically 6-8 CMOS FET's) while DRAM is made up uses single transistor plus a capacitor. So memory cell of SRAM occupies more area than memory cell of DRAM. DRAM is thus more dense and can fit more memory bits in same areas as SRAM cell.
2. However, DRAM needs to periodically refresh (hence dynamic and not continuous power supply) the charge on the capacitors of its memory cell which tends to leak with time while SRAM cells remember their logic due to cross-coupling(feedback) and continuous power supply from VDD/VSS power rails (which makes it power hungry).
3. Data can be read from SRAM at lower latency (order or more) and higher bandwidth (several orders) compared to DRAM. So SRAMs are faster than DRAM.
4. SRAM is used for very small (KB to few MB) fast on-chip L1/L2/L3 instruction and data caches on cpu's/gpus or or scratch pad memory in embedded socs while DRAM (GBs to TB) is used off chip to store high amounts of data.
5. SRAM per bit is more expensive in terms of area, power, and money compared to DRAM so SRAM is only used in small sizes (on chip or off chip) and to store data whose access time is critical to speed.DRAM us used when higher capacity is needed but speed of access is not important.
Thanks for this! Your answer is much more complete!
SRAM is much faster than DRAM
it is nice bro, in architecture system, SRAM is also called "Cache". And Cache is quickest memory in architecture system. It used to optimize the execution time of processor. Then, it is the best way to make processor runs faster.
@@duymanhnguyen8302 The quickest memory is the registers and latches in CPU. Cache built from SRAM is second fastest
@@duymanhnguyen8302 generally, you're correct, but you're confusing function and implementation. Cache is a type of memory (function), while SRAM is a technology (implementation). You could just as well implement a cache using DRAM or some other memory technology. The speed also depends on the size of the memory of course!
Appreciate the video. I had an interview for digital design (with spacex) even though I'm a computer engineer. The questions that got me are the following:
how do do know cdc data is ready when using dpram?
explain some timing constraint experience
how familiar are you with making build scripts (in vivado, libero, quartus, etc.)
explain a fpga design you have been the lead of (schematic, worst case analysis, timing analysis, embedded c, etc.)
just wanted to give you an idea of what I see in the modern workspace. I always send co-ops to your videos. keep up the good work!
Cool! I'm surprised that as a comp eng they were asking you these types of questions, unless you were applying for an FPGA job?
It was specifically for a firmware engineer position. At my job there are a good mix of people that are senior level digital design engineers that can do engineer 1/engineer 2 level skill set C programming work and vice versa for software engineers doing VHDL. VHDL modules like discrete io control, SPI, I2C, etc. may be given to a software engineer like me who knows VHDL from school if staffing resource constraints are an issue. It's usually the timing closure, top level architecture design, etc. that would be out of the SW engineer's skill set.
@@kdjohnson321 I'm also a CE graduate interviewing for RTL/Digital Design, so it's not that strange! I also think basic programming skills should be expected even if your job is to design hardware
I graduated recently and decided I wanted to work with fpgas after some experience with them during an internship, just after applying for a graduate role I watched this video and used your site to prepare for the interview and I'm happy to say it paid off and I got the job! Thank you very much for helping me achieve my goal of becoming an fpga engineer
how is the job going now?
@@akeemlouigarde4946 sorry for replying 10 months after the fact 😅 I'm still with the company and I've had a promotion, it's been an extremely satisfying job and I can easily see myself working with fpgas for the rest of my career
@@krunch3696 Hey! May I ask, what were projects or things that allowed you to land the internship in the first place?
I was always taught that the difference between Moore and Mealy was not about what state to go to next but more about the outputs at each state. In Mealy, the outputs are dependent on the current state and the inputs, but in Moore the outputs are only dependent on the current state only.
Peter Francis that’s how I remember it. In Moore the state decides output, in Mealy state and inputbdecides the output.
Yes I started learning this month
you're right
And "Mealy" is not spelled "melee". This erroneous answer seems to have caught out candidates I have interviewed, so Nandland really need to get this changed. Start with the answer the Nandland web page as its easier to fix text. But please get "model answers" right!
The way I have remembered Mealy and Moore machines is that the Mealy machine will typically require less states to implement. The input and output are shown next to each other during the transitioning state. Because the output depends on input and present state, the output will see perturbations from the input. This means we must register the output into another DFF to stabilize that output. The introduction of another DFF will cause a 1-cycle delay, but you will at least be stable.
The Moore machine, if I am not mistaken, will have "moore" states typically, but its output will always be stable because its output is only dependent on its current/present state. I hope this helps!
"Pretend like you're interviewing with me for your job, pause the video, give your answer to me. I'm not going to hear it obviously, we're not there yet with the internet but.. maybe some day". Haha, looks like we're at that day
These videos (and also your site) are extremely helpful. Just had several RTL design interviews the past week and they asked similar questions, so thanks so much man!
been listening to this vid on repeat all morning before my phone interview. thanks nand man
How did it go
@@TF-km2ls Lol they were doing everything in high level synthesis and the questions revolving HLS and hardware abstraction caught me off guard. so it didnt go well. I dont blame this video tho, its my fault for putting all my eggs into RTL concepts
@@brockfg tell us more
I think the answer for the difference of latch and ff is ff is triggered by edges of signals, and latch is triggered by signals.
Starts at 5:36 basically, great video
I got the job as a design verification engineer in the VLSI domain. Thanks to Nandland your video helped me to crack it.
Can you give some suggestions to me for design verification ? How can i get a job in verification design .and i am an ECE students doing btech .
Thank you for your great video! we have different job positions regarding FPGAs like: RTL designer, FPGA specialist, Embedded DSP designer. Each one can have different questions ❣
I believe that Sram are much faster than SDRAM, nad main difference is that Dram is much more volatile than Sram so we need to refresh periodically but in sram its automatically refreshed as there is crossed couple inverters pull the data continuously with out recharging , and can also diffrentiated by the construction of these memory
"It depends." For large sequential memory reads/writes, DRAM is faster. SRAM is faster for non-sequential "random" reads and writes. So it depends on the application.
SRAM are usually smaller compared to DRAM, but SRAM can give the word in several nanoseconds and it is easy to use with FPGA, because SRAM is very similar to FPGA’s BRAM. As for DRAM, remember timing settings in BIOS for memory modules? That is quite complicated to implement in FPGA, but possible. Some FPGAs have hardware DDR SDRAM controller for this case.
Also, nowadays there are PSRAM chips, which are pseudo-SRAM. Internally they based on DRAM, but have SRAM-like interface, combining ease of use and big size.
I knew most of the answers to these, but I always flop on interviews because I get tripped up on terminology. This video has been extremely helpful in giving concise answers for an interview format. Thank you!
Best channel about learning in depth FPGA's Ive seen this far, thanks for all your con tent!
Thank you a great introduction to FPGA I have a lot of discrete logic family experience mostly the 74 ABC families and some 4000 series (I got as far as treating them as analogue parts). I was surprised that I actually new the answers plus more detailed knowledge about how the digital blocks worked and what they are used for.
4:00 A melee machine beats the hell out of you lol
Mixed up things a little while talking about mealy and moore state machines. It's the output which depend either on the state and the input (Mealy) or only on the state (Moore). You were talking about state transitions, which depend on both variants on state and input. Maybe add a comment to the video to not confuse some newbies watching :-)
Besides, great video! :-) Liked it.
Thank you for your video! It is really helpful as I am preparing for my interview tomorrow for internship at FPGA company :)
Hlo.. Sister..
How did it end up going? I'm in the exact same boat
"Melee machine!" HAHA, that's a good laugh. It's "Mealy", "melee" is a fight.
had the same thought!
Synthesis tool - can be provided by an Independent CAD tool Vendor Such as Synopsys or Cadence. Commonly FPGA vendors can provide two options a). Their own tool like LSE for Lattice and b. third party tool e.g. Synopsys Synplicity.
Occasionally a student can try to switch between two Synthesis tools in the same FPGA setup. But Xilinx Vivado will use its default tool and this is most recommended. when you switch tools sometimes you need to provide a different timing file - TCL script. Running an RTL code in two tools is not necessarily the smartest thing to do.
*This was so helpful thanks a lot. Who else is here in 2020*
I have been writing Verilog Code since at least 1994. I finished my MSEE in 1990. I have now been coding Verilog and Matlab for almost 30 years. Its very good that you made this Video. Good questions too. I wish you add more content - one common area would be
1. Clock domain crossings - in Verilog.
2. FIFO design with Grey coded counters in Verilog - Cliff Cummings - 1994
3. AXI-4 streaming Interface - which requires 4 signals.
4. AXI-4 Slave design.
So the flow in an FPGA is Synthesis-> Map and Place and Route. The Netlist at the time of mapping does not have the RC Interconnect information.
But its very useful in terms of the DSP resources and LUT count and DFF usage and Block RAM usage. This is why doing a three part synthesis flow
provides one information in a "timed " way compared to all in flow Synthesis flow. I commonly check the Map resources Table to see if the RTL is really using too many DSP resources and BRAM.
Awesome video. Great reminder of my college VHDL courses.
GREAT VIDEO that summarizes very important info
Bus arbitration and methods of arbiter operation might be an area where you wanna add questions. Such as what is the difference between round robin arbitration and priority coded arbitrations.
I think the questions are reasonable, some answers are fine, but not all. Some answers are wrong enough to give you a bad outcome in an interview. Here are some corrections:
q3: diff flop latch
A better answer is the difference has to do with how the output gets updated. When a latch is open it is 'transparent.' Changes on the input D show up on the output Q (after some tprop). In a flop the output does not change until the flop is clocked. So changes on the input before the clock are not visible on Q. When a latch closes D will no longer effect Q, until the latch opens again.
q4 choose an fpga
FPGA's are _always_ slower and bigger than an equivalent std. cell design. It is fundamental to how FPGAs provide the re-programmable feature. E.g. a 14nm FPGA will achieve ~+500MHz in logic/processors, a 14nm std. cell design will achieve ~++2GHz, all other things being equal. This is because FPGAs implement some logic indirectly (luts, muxes, etc.) while std. cell designs implement logic directly (nand, nor, etc). This speed difference is the reason FPGAs have to provide hardened DSP blocks and the like to mitigate the performance degradation.
The main points are: ASIC/std cell's are costly to manufacture, can not be changed without re-manufacture while FPGAs have a better cost model, can be iteratively designed and can be modified even in the field.
i/o has nothing to do with fpga vs std. cell.
high mem b/w requirements have nothing to do with fpga vs std cell
tons of math operations, these are always as fast or faster, smaller, less power in a std cell design
all the applications you mention are easier to implement in a std cell design than FPGA.
q6 diff between sram dram
You should skip this answer completely and go find your own. If you gave me this answer it tells me the candidate does not understand the difference.
There is a difference between access time and bandwidth. DRAM is not faster than SRAM, do you see any cache tags or TLB's built from DRAM? Nope, all SRAM. All things being equal SRAM has more available bandwidth than DRAM due to refresh overhead and due to the row activation, column activation semantic required by the multiplexed address pins of DRAM.
DRAM bit cells are fundamentally smaller (3 or 4T cells) than an SRAM bit cell (6 or 7T cells). That is why you need to refresh DRAM, it's charge will degrade, not SRAM. 3/4T makes DRAM great for bulk RAM.
q9 what is meta-stability
Again, good question but go find another source for the answer, using this answer will not help you.
Anytime you violate the setup and or hold time of a flip flop you risk putting the flop output into a meta-stable state, i.e. it is not reliably a logic 0 or a logic 1. The flop's physical design determines how long it takes for the flop to stabilize.
The signal source, internal or external, has nothing to do with the likelihood of inducing meta-stability. If the signal is asynchronous to the clock used by your flop there is a probability of inducing meta-stability.
The risk of meta-stability is statistical, the more asynchronous the driving clock to the capture clock the more the risk of meta-stability. This is the reason dual flops are used to capture source asynchronous signals, including those crossing a clock domain. The dual flops reduce the probability of a meta-stable event to near infinitesimal.
q16 clock crossing
Fast vs slow is not the issue. Two clocks of the same frequency but not synchronously related still require meta-stable filtering techniques.
q18 melee(sic) vs moore
This is text book stuff, good question for junior people, if you are one you should have this exactly memorized:
Mealy: outputs determined by current state and current inputs.
Moore: outputs determined only by current state
I WISH YOU HAD A CHANNEL TEACHING FPGA FOR BEGINNERS. YOU ARE REALLY GOOD AT TEACHING. YOU CAN HAVE A CLASS ON TEACHING EVERYTHING ON FPGA'S . Like what is a FPGA ,real life examples of why a person would use one , what are all the pins for ,,how to program them and basic manufacture design of FPGA. I personally would be on that channel every single video...no one has that ...i have been checking for a while now. you are good are teaching
Hey thanks! But you know... this is my channel. I have a lot of videos!
@@Nandland i just realised i have started i will watch all if possible. thx you are awesome
My background isn't electronics, so this is a very useful guide for highlighting my knowledge gaps. One question I have - is the assertion that DRAM is 'larger and faster' than SRAM correct? I always thought that SRAM was faster, due to the lack of need for refresh cycles which delay read/write, and use of directly driven flip flops, rather than gate capacitance to store the bits, hence it's use in cpu cache. As a software engineer, I find the whole topic of being able to design hardware at the HDL level of abstraction fascinating. It's high enough level to not require lots of phsical knowlege, yet low enough level to understand how it maps to real hardware (or rather how it could be mapped to real hardware, outside a clever device like an fpga).
"It depends." For large sequential memory reads/writes, DRAM is faster. SRAM is faster for non-sequential "random" reads and writes. So it depends on the application.
That is a great speech and very helpful for my next interview. But at 8:14 you said that DRAM was much faster than SRAM ? I think that is SRAM faster than DRAM ? Is it right ?
Hey buddy, it's a Fantastic video, but I think you made an error somewhere. at 8:03, you said, "DRAM is larger..." If you are talking about a single DRAM cell vs a single SRAM cell, then the SRAM cell is much larger than the DRAM cell.
DRAM is not faster than SRAM because DRAM requires constant refresh to retain data and CPU cannot retrieve data from DRAM while it is being refreshed. In contrast, SRAM, since it's static, it can be accessed anytime without waiting. And because of the smaller size of SRAM, walking through the cache pages is much faster than the bigger DRAM.
I know about zero of these questions today, but it's great to have a good study guide. :)
Visited first time on this channel....Loved the question very informative
It was really useful to hear it in English. Thanks!
"Being wrong is most of being an engineer"
Man .. you got it there 😁
That’s just true for life haha... I am a neuroscientist and it’s the same lol
Thank you for your job! people like you inspire me to self-development
Excellent and very useful discussion - I am impressed
Great video... I have a tech interview in couple days. This gave me some confidence.
I recently landed a job as an FPGA engineer. They asked pretty much the basics. However, I wasn't able to answer a couple of them. Could you help me with that?
1. Using IPs(microblaze), HDL wrapping and writing C programs using the Xilinx SDK vs Doing everything using VHDL from scratch to finish - Which method is more efficient in terms of timing, area, and resources?
2. Simulation looks good, synthesis and implementation look good, a bitstream is generated and FPGA is programmed. However, the FPGA doesn't function as per requirements. How do you go about debugging starting with your bitstream?
I think these two questions are critical.
for Q2) what about timing? did the design meet timing?
1) Writing VHDL will likely be more efficient, but more time consuming.
2) I'd look for ways in which my simulation was deficient. How good is my test coverage? Are there situation I haven't covered? Does my simulation correctly represent my clocks? How well have I simulated my resets occurring? I'd try and infer possible issues from the precise way in which my design doesn't function, can I figure it out by looking through my code? Failing that I'd debug my design live on a device by adding debug in various forms, counters, capture streams etc, and hope my build time isn't too terrible.
i think you made a mistake on the sram dram part. i thought sram is faster than dram because sram uses transistors primarily for storage rather than the capacitive storage that dram uses, which takes time to charge and discharge.
I like how after he asks a question, he goes 'yeah this is basic, if yo don't understand it..you better learn it' lol
Great video, I have an interview coming up and it's nice to have a bunch of the topics I need to review in one place
thank you so much for this excellent resource
Awesome....time well spent here learning
Your answer to the difference between Latch and Flip-flop,
Another more prominent interpretation is the Latch is level triggered and Flip-Flop is edge triggered.
“Name a few flip-flops”….uhh crocs and Birkenstock….
Hired!!!
Very helpful when you need to prepare an interview!
could you do a tutorial of DDR PCIE Ethernet or something like that? i think it is widely used and very helpful for me
"Getting rid of metastability" - to be exactly:
never, but you can reduce the probability to extremely unprobable (probability reduces by a factor by each FF stage), see also MTBF.
Or to never cross clock domains of asynchronous clocks🙃
SRAM is faster,and the difference between f/f and latches we can say they both use clock but in case of latch it works as enable or disable and in case of f/f it is triggered.Correct me if I am wrong thank you
A latch doesn't need to be clocked in the sense of synchronicity, e.g. an SR latch has two stable states which can be selected simply by "clocking" either of its inputs.
I am a high school student trying to figure out some FPGA for ADC to RAM dump for a science fair project. Feel like ready for a job.
This is actually pretty good. Thanks. Great videos.
Thank you for this video! I love having interview questions with Jim Halpert :D
lol I was thinking the same thing.
Appreciate the effort, you were helpful there sir......
But u look like doug demuro of electronics and i can't unsee it
Excellent Questions to learn. If you are an interviwer than I would never got the job, lol
Thank you for sharing this awesome video.
I think there is a mistake on the question about moore and mealy FSM. I think the the main difference is the whether the output depends on the input or not, not next state.
at 19:24 DSP is to fast multiply accumulate operations? i'm not sure it i heard it correctly
Yes, multiply accumulate or MAC instructions are how DSP filters like an FIR filter are executed efficiently in hardware. Essentially you are multiplying the filter coefficients with the samples and accumulating the results likely using a circular buffer
What’s the name of the previous video he’s mentioning at the start, can’t find it!!
I thought synchronous meant that was timed with the rise or drop of the clock and a synchronous could have a clock from an external signal but was not in line with the timing...
I've heard both. I think saying Async is "not aligned with any clock" is more accurate. I find for beginners it's easier and more understandable to say sync = clock, async = no clock. But yeah maybe I should be a bit more careful here.
Great video man, thanks for sharing!
I used for in verilog to cycle through something.
Not to duplicate it, so I don't know if that's valid.
Appreciate your help! I really needed something like this.
But now I have couple of questions for you,
1- What companies, from your experience, can be good examples of a working environment in this field?
2- What do you exactly do in such a job? In boring details please..
1. Every company is different. Hard to generalize. But being an Engineer in general means that you have a lot of responsibility and control over your job.
2. You code! Lots of RTL and Testbench writing mainly. Working in the lab sometimes, design reviews with other disciplines, etc. It's fun!
@@Nandland sweet!
Thank you for great content!
I have a little bit confused in Q22. What is a DSP tile in FPGA? Can you give me a simple way to understand that? ^^ I hope I will get as soon as answer from you ^^
very informative, you earned a sub. Thanks a lot
They should change the name to melee machines because of how confusing they can be to work with. Great video
Even though these questions seem relevant, they are really like a university course exam. I'd never hire a candidate based on answers (on pretty simple) random questions. A minimum requirement today is a coding interview (and not just a typical FIR filter BS), and an actually good interview is of a problem-solving type. So giving a candidate a real life problem to think of possible implementation, to sketch a microarchitecture and to write some code example. Or find a problem in an existing design code example.
Would these questions be sufficient for an intern?
@@sj9184 Yes and no, I also wouldn't structure an interview with an intern in that way either. First, some of the questions are too basic for an electrical engineering student, some are not too relevant (you don't need to know what BRAMs, DSPs or PLLs are, you can learn that). Ofc some would make sense, but an intern should still be able to demonstrate basic coding skills (no necessarily in VHDL/Verilog), ability to think algorithmically, ability to do some basic problem-solving, ability to read documentation, etc.
haven't replied about how to prevent metastability
Not an expert, but is DRAM really faster than SRAM? Would have guessed that it is the other way around....
I want to become an fpga engineer. All I know is C and digital logic design basics. Kindly guide me.
Wonderful! Many thanks. :)
That's very helpful...
As someone who got into FPGAs just a few days ago, I can confidently say I will not be getting the job
Hahaha pull me in as well brother
I think you missed a very basic differences between SRAM and DRAM - DRMA need refresh, SRAM does not. This is significant because refreshing DRAM will tie up more clock cycles and FPGA complexity.
its very helpfull video thank you:)
There must be a lot more harder questions?
Can you explain about ASIC
Right, that's a good interview question. Or are you asking me to explain ASICs?
@@Nandland I am asking about ASIC concepts. Like CDC checking
i am working on a fault injection system
Great video! How much time do you expect the interviewee spend answering each question?
About as long as I did would be fine. A few sentences to show that you know what the interviewer is asking. You can always ask the interviewer if they want you to go into more detail. It's a conversation!
I believe Q6 answer was quite wrong. Also, the mealy vs moore answer wasn't explained correctly.
Granted I'm an EE student and likely won't be working with FPGA's when I graduate but these questions were a lot simpler than I expected, and I didn't like my FPGA course :P
You'll notice when you get to the industry, a lot of the interviewers are older guys who don't have a solid grasp of what FPGA's really are. They're either in too much of an administrative job to care about learning, or they're close enough to retirement so they don't really have to learn it. Either way, you're the next generation of knowledge. Having a basic understanding and being able to talk about digital design is what they want to hear.
Your video are so good and helpful. I appreciate that you made it!
I have a question.
I studied electronic engineering in university and got my masters degree in Korea but when I graduated I got a job as a software engineer and worked for 1 year.
I moved to the US and I realized I want to start over my career as a FPGA engineer or anything related about that position.
What do you recommand for me to study? Or for interview.
It's been a long time i haven't studied about digital so I think I should start over all basic major knowledge and a small project by myself.
Actually, I have no idea how to start a project in FPGA field if you can recommand it as well it will help me too.
I have no experience any studying or interview in US.
I will really appreciate your advice.
Great video! Do you ship the GO-Board to Australia?
Yes!
Thank u.. So much..
hey awesome video.
bawa yaar. phoda. Gori gori gori
One other really important thing you should have mentioned is . There are three major classes of timing paths on an FPGA.
a. Paths which start at a CLK pin of a flip flop and go CLK-> Q + Logic Delay and terminate on the D input of the destination DFF.
b. Timing paths which start at a Primary input and end at a D input of the first DFF it encounters - PAD delay included.
c. Timing paths which start at the CLK pin of a final DFF and end in a primary output.
All Static timing analysis works with these three classes of timing paths.
The difference between and ASIC STA and FPGA STA is the following the ASIC STA is run at slowest process, maximum and minimum VDD and maximum and minimum operating Temp. For a proper FPGA timing analysis one must run it almost like a ASIC STA.
The .sdc file is common between Synthesis and STA tool.
The types of flipflops i remember now is D flipflop, SR Flipflop, T flipflop and JK flipflop.
Concept questions are more suitable for phone screening.
Almost nothing was said about ASYNCHRONOUS LOGIC. The very first example is combinational logic, the latches mentioned are asynchronous as well. Of course, asynchronous logic should be avoided, because synthesis tools work better with synchronous logic (RTL=Register-Transfer-Level), and asynchronous logic can provide bugs, metastability and cancer (just joking).
Thanks! Which of the FPGA companies do you think have a brighter future?
it's helpful ,thx
Turns out I knew answers to most questions (except SERDES), though I made 0 FPGA designs... Probably time to create one.😸