Cadence Virtuoso:: Design of NAND Gate Schematic || Part-1.

[@laxmik7618]

Very good explanation sir, really u nailed it 👏👏

[@dr.hariprasadnaikbhattu]

Thanks and Welcome

[@shrutikkapatel]

Really very educational video. Thank you.

[@dr.hariprasadnaikbhattu]

Thanks and welcome

[@shrutikashinde1377]

Thank you sir🎉

[@dr.hariprasadnaikbhattu]

Thanks for Response

[@chayanaik1391]

Thank you so much sir for the detailed explanation with color visualization in the output...
☺

[@dr.hariprasadnaikbhattu]

Hi, you are welcome

[@pushparaj3240]

Thank you very much sir, can you upload the video to do simulation of netlist.v file using nclaunch which is generated in synthesis process.

[@dr.hariprasadnaikbhattu]

Thanks a lot
I will do with nclaunch

[@DAEE_SANJEEVINIPoonaykarbk]

Sir can you u please send me the specifications of this? I needed it for my mini project

[@dr.hariprasadnaikbhattu]

Hi, what do you mean by specification. It is just a NAND gate with four transistor with default values.

[@vlsiforrookies]

Check out full playlist link for Digital IC videos using cadence
th-cam.com/play/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE.html

[@dr.hariprasadnaikbhattu]

Thank you

[@zheniasg4878]

How to correctly build a 4-input NAND gate?🤔

[@dr.hariprasadnaikbhattu]

Hi, add another two PMOS in parallel and 2 NMOS transistors in series to the existing.

[@zheniasg4878]

@@dr.hariprasadnaikbhattu Hi, thanks for the reply! Could you tell me one more thing about the 4-input NAND, how to correctly set the width of the transistors or perhaps some other parameters in order to get the following results at the output:
Outlet capacity

[@ebtrabt]

very good video, thank you sir

[@dr.hariprasadnaikbhattu]

Thanks 🙏

[@picnicbros]

very easy to understand

[@dr.hariprasadnaikbhattu]

Thank you so much

[@sangeetamugali4654]

Sir this simulation is which technology??

[@dr.hariprasadnaikbhattu]

Hi, Simulation is done in gpdk 90nm CMOS technology.

[@sangeetamugali4654]

@@dr.hariprasadnaikbhattu sir I tried in 90nm and 45nm but wave form plots I didn't get.

[@faizangokak3355]

How to make rise time and fall time are equal if the condition given in the LAB, NAND schematic

[@dr.hariprasadnaikbhattu]

Hi, Are you asking about output

[@vlsiforrookies]

Check out full playlist link for Digital IC videos using cadence
th-cam.com/play/PLRQdEiVtIUAd_yPydulrdS9qwpuBreOZE.html

[@kirubhakaranraman2096]

hello sir did you can help how to design 3bit alu
with A*B, A+B, A-B and AxorB operation c1c0

[@dr.hariprasadnaikbhattu]

Follow the nand / nor / ex-or gates design tutorial.

[@pavitrakotyal]

very helpfull sir tku

[@dr.hariprasadnaikbhattu]

Appreciate for your response

[@kirubhakaranraman2096]

how to design multiple design

[@dr.hariprasadnaikbhattu]

Design individual schematic. Create the symbol. Then bring the any number of symbols to the new design.

[@preethirajan8995]

Thank you sir 😀

[@dr.hariprasadnaikbhattu]

Most welcome