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Sir, I am learning the basics. I don't find Cmos in the circuit. Can't understand why we call it Cmos LNA. Could you please explain?

Sir, i am getting the delay plot instead of the value what parameters I have to change to get the delay value

Sir which software is this?

Thank you sir

Sir, thank you for the reply

how to find the threshold of the CNTFET bu changing the diameter in the tool

Hello, I made a 6 -BIT binary multiplier in cadence and when I make a change for all inputs to go form 0 to 1 and plot the current through my voltage source (At VDD = 1.2 V), it appears that the current ripples between -5 and 5 Amps which is very surprising to me. Do you have any suggestions? Thank you!

Help me with how to make the partial ground for microstip rectangular antenna. It's part of my major project.

Sir please provide the download link of model file

graph is like noise signal

Sir even after attaching the mode files I'm facing an issue in the simulation of ADE Assembler. Does the assembler works in the cracked version of Cadence

I am unable to see my Assura button in layout view . Although I do have files for ASSURA41 . Can someone help ?

I am unable to see my Assura button in layout view . Although I do have files for ASSURA41 . Can someone help ?

Sir, I tried the same but the delay is negative

Sir, how can we apply such optimization for CNTFET, I tried but I am not able to view the parameters

Sir, in this design ur using Zigzig(m,0) kind of CNTFET why not the other type

how to get the 14nm technology of CMOS, can you share the link of PTM library files

Sir can you share the PTM model library files of 14nm, 16nm and 22nm

Sir, may i Know how to do parametric analysis for gain or AR plot

Super sir Thank you sir

Thank you so much sir its really helpful now im free of doubts ☺️

if I am designing a 3 inputs nor, do I do the same process for Vss and Vdd?

Thank you so much!

Dear sir, In av Extracted view only resistors are visible capacitors are not visible.!!!!!!!!!!!!

sir i tried but in the end its showing "spectre terminated prematurely due to fatal error." what's the solution

Sir your videos have been very useful! Could you please sir make video with Vitis or HLS and adding blocks from HLS into Vivado sir. Thank you.

I was using Vivado 2018.3 version and as you know when we open it on home screen there comes recent project on right side. by mistakely I closed it and now I want it back again so how to bring it back, kindly help or tell me the steps, please

can you design a whip antenna for low frequencies ??

Sir I am getting distorted output how to solve it

Sir, looking forward to you video on CML multiplexer

Can we calculate upper thershold voltage and lower threshold voltage ? Sir can you make video on this please

Sir I connected board even after implementation, I did not get the VIO and ILA are appeared after bumping the design in the board.

Sir I followed all the steps correctly but my graph not make butterfly.Please help sir

Thank you!

I am working with ZCU7104 board i followed the same procedure, bitstream is generated but after implementation ILA and VIO did not appear.

Sir can we follow the same procedure to implement the same design in different FPGA

Sir can you please provide me a research paper of this video cause I need for my college project and it's very urgent

Like!

Very nice explanation! Thanks a lot!

Hi sir, is it possible you can show us how to design cmos AND-OR-inverter + OR-AND-inverter as well. and 2:1 mux with cmos as well. thank you

Very useful thankyou ❤

sir ,how can we install finfet libraries ?please explain

sir can you explain finfet technology

how we will get 180nm library file

good explaination sir

jeeooo ustaad taaanuuu looooveee

Good explanation sir thank you very much.

The parametric simulation under tool tab is not there, what to do sir ?

one of the excellent video which is very useful.Thnk u sir❤❤❤❤❤❤

Thanks for your tutorial, it was helping me to design VLSI major project using AMD vivado 2024.1 version