Scoured the whole of YT and still got confused regarding this, yet you explained it so easily so fast ma'am, incredibly simplified and well taught maam
Mam,in c mos nandgate,what is the use of connecting two n mosfets rather than connecting it directly to the ground as that of p mos nandgate.i mean that the use of those two nmosfets has no effect.i.e the output is dependent on pmosfets.
For a NAND gate, output is 0 if both inputs are high, that means pulldown network should conduct when both inputs are 1.This happens if and only if NMOS transistors are in series. If any one of the inputs is 0, output must be 1. That means PMOS should conduct if any one of the two inputs is 0. That means PMIS are in shunt - just opposite to the NMOS connection
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You've explained every logic circuits perfectly.
Heartily grateful to you ma'am.
Scoured the whole of YT and still got confused regarding this, yet you explained it so easily so fast ma'am, incredibly simplified and well taught maam
the way u discussed was very nice...understood the entire thing clearly...keep making videos...
Thank you ma'am for the simple and good way explanation
how i get this full play list..????🙄🙄🙄
This channel is goated. You are the reason I am passing my EE classes in undergrad
maam you teach me in very easy way . i watch many video but i understood only through your lecture .
Thank you for making this so easy to understand!! You saved a lot of my time :)
ur a great teacher each students dream to have..just by one explanation urs we will understand everything.. 🙏🙏🙏..great guru ur..
Sister u explanation is gud but if u provide captions it is helpful fr us fr writing notes hope u consider it
I had no problem understanding her to be honest
Oooo thank you so much dear mam❤❤i have seeing this before two days of exams ....n i got it 😍😍❤❤once again thank u❤
This video u not put it in playlists,sis
Mam,in c mos nandgate,what is the use of connecting two n mosfets rather than connecting it directly to the ground as that of p mos nandgate.i mean that the use of those two nmosfets has no effect.i.e the output is dependent on pmosfets.
Ma'am please make a video on 3 inputs NAND AND NOR GATES BY CMOS
Muchas Gracias mi maestra para ayudándome . Que significa mucho para mí
Will u teach NA(network analysis)..
Very nice explanation mam..
Great
👍👌👍👌👍👌👍👌👍👌
brilliant video ma'am. thank you so much
Yes, really nice video, isn't it?
Our sir sent us back to learn this and come for viva or else he will roast us..after watching your video we got 10/10!!! Superb ma'am ❤️😀😀😀
How u drawn the diagram mam
Can you Draw a NAND gate using only 3 transistors?
You answering my questions well, thanks
if we will invert positions of NMOS & PMOS so it will become AND gate? Please help, thanks
I also notice this..
No, if you use an inverter at the output it will work as an and gate.
Nice presentation
Clearly explanation
Thank u ❤️❤️
Yes really nice video and nice explanation
best explication ever....thank u !
Yes, really nice video....
thanks for this wonderfull explanation
Great explaination. Thank you mam.
Yet we are where we begin...
What's piety and impiety?
Mam your teach is very good & I have one dout did you explain the ECL in next video
Shall I make video on ECL?
is the connection to ground is necessary for a 0 o/p? ie, if the o/p is neither connected to Vdd nor ground, will it give a 0 o/p?
No, output will be at high impedance state. In this case output is either 0 or 1
can u share and gate and or gate by using cmos
I will make a video on and and or gate. Shall I. ? It is very easy, connect a not gate at the output of NAND and nor gate?
Amazing Video, Thank you
Easy to understand explanation
how can I draw this structure with the help of nand truth table....
Realise the circuit using NMOS, then take complement of that network, means if NMOS is a shunt network, PMOS becomes series network and vice versa
For a NAND gate, output is 0 if both inputs are high, that means pulldown network should conduct when both inputs are 1.This happens if and only if NMOS transistors are in series. If any one of the inputs is 0, output must be 1. That means PMOS should conduct if any one of the two inputs is 0. That means PMIS are in shunt - just opposite to the NMOS connection
thank you madam😇blessings be on u
Ma'am please make a tutorial on SRAM
Shall I make a video on SRAM?
Very nice tutorial
Mam what is CMOS two four input NAND gate
2 input nand gate using cmos Ela construct chestaroo cheppandi
Can you repeat in english?
Very good explanation
woow beauty lady your tutor is very nice!! Thank you very much!
Really nice video, isn't it?
Madam can u provide notes
good and clear explanation.. Thank you mam
Yes really nice videos
mam you explain very perfect
Yes really nice explanation....
OP EXPLANATION👌👌👍
ótima explicação, obrigado!
Can you please repeat in English.....
Nice explanation Mam thank u very much
Excellent Explination mam
Nice explanation madam
Nice video....
The way you explained is good but why cant you draw the circuit while explaining rather drawing it at first
Your really great mam and thanks mam
Subtiles needed mam
Thanks for your class mam
Great explanation!
Thank u so much...
Ty madam for explanation
Your explanation good madam
Easily understandable.....
Op explanation🔥
MANY MANY THANKS
teams.microsoft.com/l/message/19:c5b22403fb4b48b98884216ddc773112@thread.tacv2/1598413137848?groupId=112929d5-7a03-4aab-897b-8cbc9e4e254f
2-input AND&OR gate explain
thanks mam
Thank u😊
🔥🔥🔥🔥❤️
TQ mam 👍
Nice
thanks you
valo hoeche
Beautiful..
thanks mate
Thank you Ms
Thanks so much mam
Tq madam 😘
Powerful lady..
Thank u mam
thanks
Thank you madam
Nice ma'am
Thank you so much
Nice video right....
Mem hindi ne samja dijiye
Super madam
thanks maam
What a explanation
Tanks mem
Circute😅😅😅😅😀😀😁😁🤣😂
NOT HELPFUL
RIP English
Nice
thank u very very much mam
thanks mam
Thank u so much.
Thanks
Thank you mam
Nice
Thank you mam
Really nice video, isn't it?