Cadence Virtuoso: NOR Gate Schematic Design || Part-1.

[@rishiprince5462]

I have done the same but i got irregular waveform instead of pulses .... what is the reason sir??

[@dr.hariprasadnaikbhattu]

Hi, check with rise time fall time, pulse width and pulse period

[@rishiprince5462]

@@dr.hariprasadnaikbhattu okay sir...Thanks for your Reply 😀

[@kunalkrantidas6442]

Very nice explanation. Isn't it required to do the transistor sizing (w/l) of pmos and nmos?

[@dr.hariprasadnaikbhattu]

Thanks for the response.
Transistor sizing is important. Since the output is not connected to any load. It works ok.

[@kunalkrantidas6442]

Sir if possible please upload some videos on monte carlo simulation in cadence🙂

[@baigsaab47]

What is the difference between ADE L & ADE XL ?

[@dr.hariprasadnaikbhattu]

ADE-XL has some advance function.

[@snehakharade4442]

In case if I want to contact regarding cadence virtuoso is there any mail id so that I can get ur help?

[@dr.hariprasadnaikbhattu]

plz use the messenger

[@PavanKumar-ii3gm]

Nor gate analog layout please explain

[@dr.hariprasadnaikbhattu]

Hi I did a videp on NOR gate. Use the below link
th-cam.com/video/X-ke0KeekQE/w-d-xo.html

[@PavanKumar-ii3gm]

@@dr.hariprasadnaikbhattu
Thanks sir

[@lifestoriesofAathi]

I am getting an error while simulating

[@dr.hariprasadnaikbhattu]

Hi, what is the name of error

[@lifestoriesofAathi]

@@dr.hariprasadnaikbhattu That was rectified. I have doubts regarding layout. My transistors are not as clear as yours while generating. What is the reason?

[@SAhellenLily]

Thank you

[@dr.hariprasadnaikbhattu]

Welcome for the appreciation.

[@tanmayjoshi1810]

Thanks Sir

[@dr.hariprasadnaikbhattu]

You are Welcome