Is there a crack version of cadence virtuoso software to create this layout? I am a student who wants to practice it. There doesn't seem to be a free version to practice with
Sir please help me sir, Where can I find pass transistor sir I mean that transistor name sir like bsimp4 like that sir. I have Shannon adder by using pass transistor sir but I don't where it is sir
In the cell view when i opened or2 gate it is not visible sir. I mean when i am editing input variable name at that time the image or or gate had gone sir When i reopened it Even though it showing empty image sir
I got the following error after DRC run. Any solution for this ? " Minimum dimension of an NW region not connected to the most positive power supply is 2.10um. Need to be changed depending on your power supply name In this case the most positive voltage "
in 12:22, my nmos isnt like yours, its showing 3 metal1 pads and theyre not snapping in
Hi, Check in Layout. Go to Options--> Editor
then enable the 1) Abut Server 2) Qcell Auto Abutment,
Sir, I'm new to this and you helped me so much. Thank you!
Thanks a lot for the response
I ❤. Quick question, how did you rotate the path when you were wiring the second gate?
Kindly mention the time line of the video. So that I can answer
in 3:57 how did you pair both pmos ? it doesnt mean that drain of pmos1 and source of pmos2 is connected ?
Hi, I have consider both as Drain and connected then as one you can see that in schematic.
if I am designing a 3 inputs nor, do I do the same process for Vss and Vdd?
Hi, vdd and vss remain same only the topology of transistor changes
why can't I combine two series nmos like you? It still has three pins after
Hi, in display options enable abutment
@@dr.hariprasadnaikbhattu I can't find this option
I am unable to see my Assura button in layout view . Although I do have files for ASSURA41 . Can someone help ?
Hi, check you have Assura or Calibre for DRC and LVS
Is there a crack version of cadence virtuoso software to create this layout? I am a student who wants to practice it. There doesn't seem to be a free version to practice with
Hi, check TH-cam. Some are providing the links
@@dr.hariprasadnaikbhattu yes, can you give me some of those links? I really want to learn layout while I'm still studying
There is no assura option in my cdence. How to proceed further sir?
Hi, NO assura option means there is Calibre options to perform the DRC
Sir please help me sir,
Where can I find pass transistor sir
I mean that transistor name sir like bsimp4 like that sir.
I have Shannon adder by using pass transistor sir but I don't where it is sir
Hi, BSIM4 are the model or technology files used to simulate MOS circuits.
They are not free. Instead use the ptm models
ptm.asu.edu/
@@dr.hariprasadnaikbhattu
Thank you so much sir
How to know when pmos or nmos is detached or integrated sir ?
Whether it is schematic or layout. In schematic they are detached. But in layout PMOS or NMOS are integrated. So need to detach
@@dr.hariprasadnaikbhattu Thank you sir.
Sir in gpdk90 where can we find assura option
Assura is available in Layout XL
Sir can you help me sir 🙏🙏
Layout is missed sir
When i was editing the variables in OR GATE
How can I reget it sir 🙏
1) First open schematic design
2) Launch (from schematic) -->Layout XL--> Open Existing
Hope this will help you.
In the cell view when i opened or2 gate it is not visible sir.
I mean when i am editing input variable name at that time the image or or gate had gone sir
When i reopened it
Even though it showing empty image sir
How to load file in assura technology..? Sir
Hi assura technology file comes with gpdk. Use library path editor
So nice thanks sir
Thanks 👍
Thank you so much sir!!
Thanks for the Support
I got the following error after DRC run. Any solution for this ?
" Minimum dimension of an NW region not connected to the most
positive power supply is 2.10um.
Need to be changed depending on your power supply name
In this case the most positive voltage "
Try to increase the nwell region
since it's layout it takes some time. yahhh bro I totally agree with you.
You are Welcome
Hi Sir,
This is really helpful!
If you can provide a way to download the cadence virtuoso crack, it will be really helpful!!
Hi, try the website www.getintopc.com
Thanks
Welcome
Thank you sir
You are welcome
Welcome
@@dr.hariprasadnaikbhattu Hi sir how to estimate the area ? do we estimate area in schematic or in layout. please explain. thank you
Sir am doing for comparator circuit thats too big. I have some doubts. Can you share your mail id?
How can I help you?
@@dr.hariprasadnaikbhattu
My doubts are in layout sir. I am struggling how to do perfect layout. For me overlapping happens.
@@dr.hariprasadnaikbhattu i followed your 90nm inverter layout. While am trying for comparator in in 180nm i couldnt place vdd and vss as rails.
@@பிருந்தாதஞ்சை madam you need to place vdd and vss in schematic also
@@dr.hariprasadnaikbhattu
Yes sir i gave. I follwed your video only.While fixing rails it says other pins will go and it cannot be undone.
Please help me sir
I have replied
psub stamp error mult
Check the well dimensions
Please help me sir
I have replied