Hey Karthik, In timing diagrams the enable signal is pulse signal. In your explanation you considered that clk A frequency is lower compared to clk B frequency. So the enable pulse in not missed in front of synchronizer. If the clk A frequency is high compared to clk B, then we will miss that pulse in receiving domain. OR is this the limitation of this synchronizer.
Hi Karthik. Happy Morning. My doubt was that why data is not being fed through synchronizer and directly fed to clock domain B and instead only an enable signal is being fed to syncronizer. When data was single bit it was fed to synchronizer while crossing the clock domains in Toggle syncronizer and 2 Flipflop syncronizer.
Hi Karthik, Your videos was really helpful and you r explaining very well. Can u share the link of different types of synchronizer. And Can you explain reset synchronizer. Thanks
May I know...why data should not be changed frequently..if it happens,how it will affect the output.if you explain this problem with timing diagram,it would be much easy to understand for me.Thanks for sharing your knowledge😊
If we change input frequently , then it will interfere with already processing data , so may cause metastability. Thanks for asking, good luck, good health 👍
Thanks for ur explanation bro...but still I am not getting..if you don't mind,can you make a timing diagram for that problem?and can you send it to my mail id kjenith8@gmail.com...Thanks for ur help in advance💐😊
Hey Karthik, In timing diagrams the enable signal is pulse signal. In your explanation you considered that clk A frequency is lower compared to clk B frequency. So the enable pulse in not missed in front of synchronizer. If the clk A frequency is high compared to clk B, then we will miss that pulse in receiving domain. OR is this the limitation of this synchronizer.
Hi Karthik. Happy Morning. My doubt was that why data is not being fed through synchronizer and directly fed to clock domain B and instead only an enable signal is being fed to syncronizer. When data was single bit it was fed to synchronizer while crossing the clock domains in Toggle syncronizer and 2 Flipflop syncronizer.
Hey are are you sending multi bit data through a multiplexer? Are u using PISO?
It's very helpful, Thank u karthik
Thank you so much for commenting ,
Can you suggest a topic for next video , if I know that I can make it for you , good luck 👍
Very informative video
Namaste 🙏 amit , thanks ,for topic you can refer research papers on internet , good luck & great health 👍😊
Hi Karthik,
Your videos was really helpful and you r explaining very well. Can u share the link of different types of synchronizer. And Can you explain reset synchronizer. Thanks
You can rest of synchronizers on my channel playlist clock domain crossing.
If you have any questions, please feel free to comment 👍 good luck 👍
Thanks a lot for ur quick reply. Pls don't mind and share the link here. I am not able to find. Thanks
@@KarthikVippala Thanks a lot
Your welcome, good luck 👍
You don't need a MUX. Just use a DFF with an Enable signal.
May I know...why data should not be changed frequently..if it happens,how it will affect the output.if you explain this problem with timing diagram,it would be much easy to understand for me.Thanks for sharing your knowledge😊
If we change input frequently , then it will interfere with already processing data , so may cause metastability.
Thanks for asking, good luck, good health 👍
Thanks for ur explanation bro...but still I am not getting..if you don't mind,can you make a timing diagram for that problem?and can you send it to my mail id kjenith8@gmail.com...Thanks for ur help in advance💐😊
@@jenithk6769 I will do it , but it will take time
Take ur own time bro..but plz never forget me😊
For sure👍
Hello sir, when do we use handshake synchronizer and mux synchronizer?
Handshake is used when we want acknowledgement , but actually it depends on specific design requirements whether to use this or other synchronizer.
Can we generate o/p such as every positive pulse of I/p will stretch by 1 clk pulse then 2 clk pulse and soo on .. please guide
sir, do we have to use 2 bit mux in this example?
Is this synchronisation applicable for fast to slow clk domain ?
what all different technique used in CDC and why and where it is used
Hey Prateek , thanks for asking
You can checkout synchronizer playlist on my channel for different types of CDC techniques
Sir, which book should I follow for this topic?
please check for papers on it and enjoy reading . Thanks for the asking , good luck & great health, Take care :)
can we use mux instead of on chip clock controlller
Namaste🙏,Can you be little specific, didn't get u, thanks for asking
Hi sir,please tell way to learn questa cdc tool.
Thanks u so much @karthik vippala
Hey uday ,
Can you suggest any other topics .
Thanks for asking 👍
@@KarthikVippala I have completed my seminar...thanks for you because ur videos were basic sources to me and helped me a lot
I am happy that I was helpful to you 👍
I think u better start videos on SoC topics
@@uday5786 can you be little specific on what topics should I start
Brother, please don't use that ascent, it is hard for us to understand.
Improving on it🙏