VLSI : synchronous reset vs asynchronous reset active low

What is synchronous reset and asynchronous reset
explain about synchronous and asynchronous reset
reset removel and reset applied
synchronous d flip flop verilog code
asynchronous d flip flop verilog code
d flip flop with synchronous reset
d flip flop verilog code
synchronous reset and asynchronous reset

[@Jakefromstatefarm56503]

I LOVE YOU BRO! MY EXAM IS IN 30 MINUTES AND NOBODY COUD EXPLAIN THIS EXCEPT FOR YOU!! I WATCHED MANY TH-cam VIDEOS AND TALKED WITH MASTERS IN ENGINEERING AND THEY COULDNT TELL ME!!!

[@VLSI-learnings]

Thanks

[@PINTUKUMAR-rv8po]

Undoubtedly best lecture on TH-cam

[@VLSI-learnings]

Thanks

[@prakharawasthi1419]

thanks brother i seaching for this simple type of explanation, thanks for introducing it.

[@abhaygautam2487]

Please upload more video ..very helpful for interviews

[@VLSI-learnings]

sure

[@sekharece413mtech]

Sir you're video are insight ful and very useful for , as studnet i have a query why fpga design are synchronous and why STA is done on only synchronous design .

[@swapnilsrivastava2853]

perfect explanation

[@VLSI-learnings]

Thank you

[@Tamilss2510]

Thank you for the clear explanation .
Is there any possibility to synchronize the asynchronous inputs ? if so where do we need it ? could you please clarify

[@VLSI-learnings]

wait i will post more video's

[@nirpjotkaur7700]

As the reset removal is synchronous in both types of resets. If reset is removed near active clock edge, what is reset removal problem in both asynchronous and synchronous reset?

[@VLSI-learnings]

Flop will go to metastable when reset generated in other clock domain

[@akashwayal8797]

Excellent!

[@VLSI-learnings]

Thank you

[@rajithanookala9234]

Can u please explain timing path between latch and flip flop....

[@VLSI-learnings]

latch is combinational loop and delay infinite . if latch is there in the design that path timing will not calculate for that particular path . we declare false path in synthesis .

[@susheelapatgar3640]

thank you sir

[@VLSI-learnings]

welcome

[@mohammedjawadsaleem1186]

Syc Guru

[@VLSI-learnings]

Thanks

[@VLSI-learnings]

thanks

[@Harshitha-mm7ki]

! reset means?

[@VLSI-learnings]

If reset is low that logic becomes 1