Many of my friends say, what's so special in PCB designing? you just connect two pins with copper wire and there's no big deal about it. And that is when I show your videos and how meticulously routing must be done. Thanks for awesome content again, loved it.!!
It's an art! The puzzle where you have to make compromises and trade offs, so many restrictions to take into consideration, like mechanical limitations, cost, heat, signal integrity, EMC, etc..
You should educate him on EMC and Signal Integrity next! 😅 It's like saying what's the big deal with power lines? We just take big wires and connect them on the poles. 😅
Some NC pins on the eMMC chip can actually be used to route through. Allows to use wider traces without the need to go between the BGA pads. There are app notes in existence on the subject.
thank you so much for this video! very perfect timing as my current project involves caBGA. I just started a job as a junior pcb design engr so I have so much to learn and improve. your videos have been so helpful really.
This kind of layer stackup planning and HDI board routing needs a lot of experience. Excellent tutorial and thank you for sharing your knowledge with us.
Thanks, Mr. Feranec. I always watch your videos and compare the thing you talk about with my previous work. I always find sth I did wrong and take notes about what you said in order not to remake the same mistakes. It is a great opportunity to learn from you!
Another great video! From my opinion, the layout in this example looks neat and well considered. The engineer who designed the board is far more than a "junior" designer 😄
Thank you Robert for another fantastic, informative video. Really appreciate how you show in detail a board design in a CAD tool going over the layers, vias and planning. Thanks for showing real examples and referencing other valuable videos and documents. Superb tutorial! Appreciate you sharing your expansive knowledge with us.
Thanks for sharing all that info Robert! uVias are really helpful in designs like this! Sometimes it is convenient to also use skip uVias to go from L1 to L3 for example (also stacked uVias but I think they are a bit more expensive and sometimes a bit less reliable). You just have to keep an eye on the aspect ratio, and keep it up to 0.75 or maybe 0.8 (drill/depth) as a general rule for uVias in order to have a good manufacturability and keep the cost as low as possible. When it comes to low pitch BGAs like
Very helpful video! I am trying to create a SBC using the Allwinner A64 chip and haven't had much experience working with BGAs. Thanks you for the insight.
Great video Robert! Via aspect ratio is not really anything to do with drilling - it's to do with ensuring consistent and reliable plating all the way down through the hole. Some like to specify a "minimum plating thickness in holes" on the fabrication notes, e.g. 20 um.
Thank you Nick. PS: Yeah, I have explained via aspect ratio in some other videos, I didn't want to go too much into details in this video. It is sometimes difficult for me to decide what to explain in multiple videos and how to do it. But thank you for pointing this out it may be helpful for some people.
Robert Thanks for yet another great video. Your videos are always a pleasure to watch and informative. And they greatly assisted me in a range of designs i done in altium. As I am about to embark on a design using a 400 pin BGA this is once more useful. One question on the via under the BGA would you tent them or not? What your experience on this
Really cool videos. I am pretty sure the drawbacks of via in pad can be addressed by proper layout and mix of vias depending on purpose. I think it highly depends on stack up, but in general it is possible to make via in pad layout to keep solid (non perforated) ground and power planes.
I'll have to watch this a few more times... Thank you, I have been occasionally searching for a good fanout video since Charles Pfiel's video disappeared from Mentor's website. Any chance you can do an interview with him or something to help fill in more of that missing video?
Great Video... As you said that micro vias cannot be drilled through many layers can you please explain how you used those from 1 to 10 layers for orange data lines... Did you use multiple vias like from 1 to 3, 3 to 6 and so on to connect it from layer 1 to layer 10?
17:40 How does something like swapping pins work with your day job Robert? I assume you do mostly subcontracted work (and consulting). How flexible are the stereotypical set of constraints? Are most jobs based on fresh designs or are they revisions with preexisting software? I imagine preexisting software constraints, the number of nets, and PCB layer constraints are the primary factors you use to bid on a contract. In my mind, I'm comparing how I ran my autobody shop, and the complex way I priced repair jobs based on the time it took me to do each step of a repair. I learned many lessons the hard way, like how all colors are not equal, and the amount of force/effort it takes to damage a structure will require an equal amount of force to reverse regardless of how small/insignificant the damage appears on the surface (AKA always look behind the panel, at the real frame structure). Oh, and NEVER estimate jobs in the rain....
For new designs (like thisone) we are free to swap pins on connectors. Swapping pins on CPU - I would not do that for boards running OS as the pins are tight up to software and you would have to re-write a lot of existing stuff. For FPGA, I know that many people swap the pins (I do not do FPGA designs much).
19:30 How does one differentiate between net color and layer color? Earlier you mentioned the disappointment with using via-in-pad because it limits the fan-out options. I suppose you were referring to through hole via-in-pad? Why not micro via in pad?
1) I intentionally used full color override. You can change settings to see also layer color if you need (it is in system preferences -> PCB Editor -> Board Insight Color Overrides) 2) micro vias would not help me as they can't go too deep into PCB
Most awaited video, thanks. I have one doubt if you have no space between vias on inner layer, why not delete unused pads of vias on inner layer? It will help to create more space between vias on inner layer. And you used micro vias for specific lanes why not all signals. Is the cost of manufacturing depends on the count of micro vias? Thank you sir.
Thank you Sujit. Yes, you can delete the unused pads, just be careful, you still need to keep the minimum hole to copper distance we were talking about in the previous video. I have used this technique in some very packed boards. If you would use uvias an all layers, your PCB would be very expensive to manufacture - not because of number of microvias, but because of number of layers they are located on. For example when they will be manufacturing the board from video, they need to make 8 layer board first with all buried vias - once the 8 layer board is finished, they need to stick one single layer on each side of the PCB (they will make 10 layer PCB) and make the uvias. And after that, they have to stick another 2 layers on each side of the pcb and drill another microvias. After that they still need to drill the through hole vias. Each this process cost a lot of money as basically you need to go through PCB manufacturing process again and again multiple times.
Do you use unconnected pad suppression? Orcad allows you to remove copper pad on internal layers that aren't used. This will save you space on your routing channels or use a larger drill.
Anther great video, thank you. Couple of comments/questions. Doesn't Micro visas mean small drill and generally used with blind/buried visas? And aren't you using blind micro via layer 1 to layer 2 and then a buried micro via from layer 2 to later 3? And why not use stacked visas instead of stepping away from via on layer 2? For example, discussion before 12 min mark.
Good Question ! I want to read the answer too :) ( Edit he did not answer your question may be because already answered same or similar question below with Sujit rokde question ;) )
Blind via means blind on one end. Micro Via usually means drilled by laser. Blind via can be also microvia. Stacked vias are more expensive and can have more problems with reliability: th-cam.com/video/FM3pRM0CxGw/w-d-xo.html and this is also very good: th-cam.com/video/f6_svRNJYls/w-d-xo.html
@@RobertFeranec An interesting video would be on the topic of using BGAs like this on boards where you can only have parts on one side of the PCB - I've had to do this several times, though never for a BGA. This would effectively remove the option of putting the caps directly under the BGA.
Hello Robert, I have a question about time 25:30, what the signal that engineer want to place on layer 10 which is a plane between two solid ground layers? Thank you.
Cautionary tale: when using blind vias in pads for BGAs, trapped gases may inflate the balls during reflow and cause them to short. I don't how much of a problem this is with through vias though.
Hello Robert. Good video! But I think good designer must know where is the end of manufacturing capabilities for each VIA type. And that knowledge must came not from reference designs but from manufacturing spec. sheets. I saw there is some fabs, which can drill holes less than 0.2mm. For my old desings with 1.0mm pitch BGA (FGG484) I always used 0.2mm and have no isues to manufacture in the EU or PRC :)
Very inspiring content again! Small question: How useful/efficient is Altium automatic fanout function? I guess, it requires very careful/complicated rules definition to work for large BGA... Even gave a try?
Do you have a video or info about minimum clearance of components? I am currently wondering about How close can two passives be? say, 0402s, and still not sweat about PCBA or how close a big inductor or cap can be to a small chip or passive?
Hi Robert, while i was watching the fan-out vid, i was thinking about what you was saying about the decoupling capacitors and the amount of space required to position them. whats to stop the chip manufacturer from adding a partial decoupling layer which uses bridging vias to connect to an increased pcb area local to the underside of the BGA.. this could be still be fully decoupled but allow a huge plane just for the capacitors and other power components. I have never seen such a thing, perhaps it exists? the layer would be added over the bottom layer, like an say a rectangle or square and only have the vias for decoupling passing through it. sounds complicated but i cant see why not. its just another layer. and could be controlled just the same as normal layers. so a say 6 layer board could have an additional localised two layers.
That's a little silly, "holes" appear when you mix via in pads and vias out of pads together, you can as well say that vias out of pads are creating hole if you try to put some in a design with all vias in pads, spacing remains the same no matter which way you choose, but be sure to choose one way, don't mix both. Sadly, no all BGA chips have enough spece to put capacitors, even if you choose cross pattern.
Regards from Czech Republic. Awesome video! I have one question. Whats your View Settings? You have all layers shown on bottom bar, and you view only one layer (with multiple net colors) then you click to another layer, and the view change only to another layer atc. I wonder how do you set it. Maybe, it would be a great idea for another video.
Dakujem. I am using Single Layer Mode (SHIFT + S, try press multiple times). For solid colors, go to System preferences -> PCB Editor -> Board Insight Color Overrides -> Solid
Oh, you have changed the camera. No more wide angle, telephoto lens, nice portrait look. BTW IMX8 is a s****y SoC, so many power rails, so hot under load.
Thank you Alekcej. I a m very happy that some people are noticing my new camera setup :) PS: iMX8 - Thank you very much for pointing this out. From our previous experience with iMX6, we are careful about heat distribution, but I will be even more careful now.
About GND or Power plane between vias, a manufacturer suggested me to left out the ring of via on these layers, in order to maximize the space between two drilled holes. Anyone knows if it is a reliable practice? Thanks.
Can you please tell the name of the PCB fab which manufactures microvias for "a little bit more money"? Because all the fabs I know of the difference in price between thru-hole vias only and microvias is more like 2 times or more. If it not some kind of commercial secret, can you please tell the prices for both options? The fab I currently use makes 8 layer thru-hole only boards for ~220$ for 10 boards 10x10 cm with 3/3 mil traces and 0.2/0.35 mm vias. But they can't manufacture microvias, and all fabs I know of that do are massively more expensive.
Thank you Robert for a great Video ! , if uVIA is so much better why not use them for the whole bga Fanout ?? i think if you have 1 uVia or 100 uVias its still cost the same . Also i have heard that uVia are slightly worse when it comes to reliability (This is what they tell us in our work place) is it true ??
Thank you Eyal. PS: For power pins I prefer to use through hole VIAs (bigger and better connection to power). We have not had problems with uVIAs (in the designs where we use them now), but I have seen some presentations especially about stacked VIAs and lower reliability. I think, we were talking about that a little bit also here: th-cam.com/video/FM3pRM0CxGw/w-d-xo.html
@@Kilohercas the big capacitors what I needed to fit there are 0402, the small one are 0201, but we needed higher value - that is why we needed the cross under the BGA.
If mixed, one characteristic of via in pad observed is solderability issues where the via consumes solder reducing amount of solder for the ball to pad connection. Also applies to other SMT connection types. If they are all via-in-pad variability is gone. Stencil apertures should be adjusted probably.
After applying the rules from the Xilinx document for 0.5mm pitch BGAs, Altium only places the outer two rows... Do you know what is causing this? (Its the iMX8M Nano)
Who knows what NXP will come up with. I have mixed feelings from their products and marketing. They have some super successful processors and then some failures and experiments. And if they have something successful, then they use the same name for next 10 processors which are totally different or not compatible with the successful one. It's then complete mess in their product lines.
Sir can you help with me snapdraogon apq8016 fanout in Altium? I've been working on this project for past 2 weeks but I'm facing trouble while fanout. It would be really great if I get a visual for that. Thank you, Pooja
Please go through the below link, maybe you got something useful. designhelp.fedevel.com/forum/test/pcb-layout/10296-qualcomm-snapdragon-apq8016-fanout
So real people design these types of boards? I though only Martians could do it since I still didn't manage to route a board that has one Arduino two resistor and one transistor
![สาวเมืองเพชร - ธีเดช ทองอภิชาติ [Official MV]](http://i.ytimg.com/vi/kEt7F9PvO3I/mqdefault.jpg)
Many of my friends say, what's so special in PCB designing? you just connect two pins with copper wire and there's no big deal about it. And that is when I show your videos and how meticulously routing must be done. Thanks for awesome content again, loved it.!!
Thank you Gudimetla. PS: Yeah, when I was starting with hw design, I also thought it is only about connecting pins :D
@@RobertFeranec :)
It's an art! The puzzle where you have to make compromises and trade offs, so many restrictions to take into consideration, like mechanical limitations, cost, heat, signal integrity, EMC, etc..
You should educate him on EMC and Signal Integrity next! 😅 It's like saying what's the big deal with power lines? We just take big wires and connect them on the poles. 😅
@@alexanderquilty5705😂😂
Blurring the bookshelf in the background makes the video seem crisper. Nice.
Eminent, you are the first one pointing this out. I was curious if someone will notice that I updated my recording setup. Is it better now?
@@RobertFeranec It's a lot better and more professional looking in my opinion.
@@jamesm6951 Thank you
Some NC pins on the eMMC chip can actually be used to route through. Allows to use wider traces without the need to go between the BGA pads. There are app notes in existence on the subject.
thank you so much for this video! very perfect timing as my current project involves caBGA. I just started a job as a junior pcb design engr so I have so much to learn and improve. your videos have been so helpful really.
Thank yo very much Az
This free knowledge content you won't find them everywhere,thank you very much Robert for your efforts
This kind of layer stackup planning and HDI board routing needs a lot of experience. Excellent tutorial and thank you for sharing your knowledge with us.
Thank you very much Guarav
Thanks, Mr. Feranec. I always watch your videos and compare the thing you talk about with my previous work. I always find sth I did wrong and take notes about what you said in order not to remake the same mistakes. It is a great opportunity to learn from you!
Thank you Mustafa. PS: I like your approach.
Robert,
excellent as always, thanks for the effort that you put into these posts.
Thank you very much Tom. I am very happy you like the videos.
Another great video! From my opinion, the layout in this example looks neat and well considered. The engineer who designed the board is far more than a "junior" designer 😄
Thank you Robert for another fantastic, informative video. Really appreciate how you show in detail a board design in a CAD tool going over the layers, vias and planning. Thanks for showing real examples and referencing other valuable videos and documents. Superb tutorial! Appreciate you sharing your expansive knowledge with us.
Thank you very much
Again Thank You for such an insightful and knowledgeable video. It really helps the fellows out here.
Thank you Aniket
Thanks for sharing all that info Robert!
uVias are really helpful in designs like this! Sometimes it is convenient to also use skip uVias to go from L1 to L3 for example (also stacked uVias but I think they are a bit more expensive and sometimes a bit less reliable).
You just have to keep an eye on the aspect ratio, and keep it up to 0.75 or maybe 0.8 (drill/depth) as a general rule for uVias in order to have a good manufacturability and keep the cost as low as possible.
When it comes to low pitch BGAs like
Thank you giannis. PS: I agree with your comments
Every video you made is masterpiece
Thank you very much Chao Chang
You have created the best video of BGA fanout. Thank you
Very helpful video! I am trying to create a SBC using the Allwinner A64 chip and haven't had much experience working with BGAs. Thanks you for the insight.
Thank you Aetheris
Great video Robert! Via aspect ratio is not really anything to do with drilling - it's to do with ensuring consistent and reliable plating all the way down through the hole. Some like to specify a "minimum plating thickness in holes" on the fabrication notes, e.g. 20 um.
Thank you Nick. PS: Yeah, I have explained via aspect ratio in some other videos, I didn't want to go too much into details in this video. It is sometimes difficult for me to decide what to explain in multiple videos and how to do it. But thank you for pointing this out it may be helpful for some people.
Another great, super useful video.
Thank you very much Robert
Thank you Kerem
Esse e o melhor canal sobre layout de pcb
Thanks a lot Robert for quality technical information.
Thank you very much Chethan
Superb sir,
A Lot of things are there to learn for Junior Design Engineer like me...
Thanks for sharing
Waiting for your next video.
Thank you very much Vinod
Robert Thanks for yet another great video. Your videos are always a pleasure to watch and informative. And they greatly assisted me in a range of designs i done in altium. As I am about to embark on a design using a 400 pin BGA this is once more useful. One question on the via under the BGA would you tent them or not? What your experience on this
thanks for great tips!. One more thanks for your fun narration :D
Thank you Ahmet
Really cool videos. I am pretty sure the drawbacks of via in pad can be addressed by proper layout and mix of vias depending on purpose. I think it highly depends on stack up, but in general it is possible to make via in pad layout to keep solid (non perforated) ground and power planes.
Thank you movax20h
Thank you for your job. Very clear.
Thank you very much Remi
I'll have to watch this a few more times... Thank you, I have been occasionally searching for a good fanout video since Charles Pfiel's video disappeared from Mentor's website. Any chance you can do an interview with him or something to help fill in more of that missing video?
Thank you, Robert!!
Great Video...
As you said that micro vias cannot be drilled through many layers can you please explain how you used those from 1 to 10 layers for orange data lines... Did you use multiple vias like from 1 to 3, 3 to 6 and so on to connect it from layer 1 to layer 10?
17:40
How does something like swapping pins work with your day job Robert? I assume you do mostly subcontracted work (and consulting). How flexible are the stereotypical set of constraints? Are most jobs based on fresh designs or are they revisions with preexisting software?
I imagine preexisting software constraints, the number of nets, and PCB layer constraints are the primary factors you use to bid on a contract.
In my mind, I'm comparing how I ran my autobody shop, and the complex way I priced repair jobs based on the time it took me to do each step of a repair. I learned many lessons the hard way, like how all colors are not equal, and the amount of force/effort it takes to damage a structure will require an equal amount of force to reverse regardless of how small/insignificant the damage appears on the surface (AKA always look behind the panel, at the real frame structure). Oh, and NEVER estimate jobs in the rain....
For new designs (like thisone) we are free to swap pins on connectors. Swapping pins on CPU - I would not do that for boards running OS as the pins are tight up to software and you would have to re-write a lot of existing stuff. For FPGA, I know that many people swap the pins (I do not do FPGA designs much).
Great! Thank you so much!
Good explanation
Thank you Nasib
@@RobertFeranec all your video's are excellent.. actually i have started my career in layout designing with the help of your video's..
@@nasibkj880 Thank you Nasib. I am very happy you found the videos useful.
19:30 How does one differentiate between net color and layer color?
Earlier you mentioned the disappointment with using via-in-pad because it limits the fan-out options. I suppose you were referring to through hole via-in-pad? Why not micro via in pad?
1) I intentionally used full color override. You can change settings to see also layer color if you need (it is in system preferences -> PCB Editor -> Board Insight Color Overrides) 2) micro vias would not help me as they can't go too deep into PCB
Most awaited video, thanks. I have one doubt if you have no space between vias on inner layer, why not delete unused pads of vias on inner layer? It will help to create more space between vias on inner layer.
And you used micro vias for specific lanes why not all signals. Is the cost of manufacturing depends on the count of micro vias?
Thank you sir.
Thank you Sujit. Yes, you can delete the unused pads, just be careful, you still need to keep the minimum hole to copper distance we were talking about in the previous video. I have used this technique in some very packed boards. If you would use uvias an all layers, your PCB would be very expensive to manufacture - not because of number of microvias, but because of number of layers they are located on. For example when they will be manufacturing the board from video, they need to make 8 layer board first with all buried vias - once the 8 layer board is finished, they need to stick one single layer on each side of the PCB (they will make 10 layer PCB) and make the uvias. And after that, they have to stick another 2 layers on each side of the pcb and drill another microvias. After that they still need to drill the through hole vias. Each this process cost a lot of money as basically you need to go through PCB manufacturing process again and again multiple times.
@@RobertFeranec thank you sir, good explanation. I need to learn lot of things from you 👍👍👍
Do you use unconnected pad suppression? Orcad allows you to remove copper pad on internal layers that aren't used. This will save you space on your routing channels or use a larger drill.
Anther great video, thank you. Couple of comments/questions. Doesn't Micro visas mean small drill and generally used with blind/buried visas? And aren't you using blind micro via layer 1 to layer 2 and then a buried micro via from layer 2 to later 3? And why not use stacked visas instead of stepping away from via on layer 2? For example, discussion before 12 min mark.
Good Question ! I want to read the answer too :) ( Edit he did not answer your question may be because already answered same or similar question below
with Sujit rokde
question ;) )
Blind via means blind on one end. Micro Via usually means drilled by laser. Blind via can be also microvia. Stacked vias are more expensive and can have more problems with reliability: th-cam.com/video/FM3pRM0CxGw/w-d-xo.html and this is also very good: th-cam.com/video/f6_svRNJYls/w-d-xo.html
tnx so much for the great content
Great video! Thanks!
Thank you David
@@RobertFeranec An interesting video would be on the topic of using BGAs like this on boards where you can only have parts on one side of the PCB - I've had to do this several times, though never for a BGA. This would effectively remove the option of putting the caps directly under the BGA.
@@davidgustafik7968 I have not done anything like that yet ... I would be worried about reliability.
Hello Robert, I have a question about time 25:30, what the signal that engineer want to place on layer 10 which is a plane between two solid ground layers? Thank you.
Another Great video , thanks for this video sir , you are inspiration of many PCB Layout Engineers.
Thank you very much Haribabu
@@RobertFeranec no one can explain like you Sir , the way of explanation is very clear and able to understand easily
Cautionary tale: when using blind vias in pads for BGAs, trapped gases may inflate the balls during reflow and cause them to short. I don't how much of a problem this is with through vias though.
Hello Robert. Good video!
But I think good designer must know where is the end of manufacturing capabilities for each VIA type. And that knowledge must came not from reference designs but from manufacturing spec. sheets.
I saw there is some fabs, which can drill holes less than 0.2mm.
For my old desings with 1.0mm pitch BGA (FGG484) I always used 0.2mm and have no isues to manufacture in the EU or PRC :)
Very inspiring content again! Small question: How useful/efficient is Altium automatic fanout function? I guess, it requires very careful/complicated rules definition to work for large BGA... Even gave a try?
I never use it. COPY and PASTE works well for me as my fanout is usually more complicated than what automatic fanout would create.
Do you have a video or info about minimum clearance of components?
I am currently wondering about How close can two passives be? say, 0402s, and still not sweat about PCBA
or how close a big inductor or cap can be to a small chip or passive?
Ricardo, I do not. However I made a note on my TODO list of possible future videos. Thank you for your tip.
Hi Robert,
while i was watching the fan-out vid, i was thinking about what you was saying about the decoupling capacitors and the amount of space required to position them.
whats to stop the chip manufacturer from adding a partial decoupling layer which uses bridging vias to connect to an increased pcb area local to the underside of the
BGA.. this could be still be fully decoupled but allow a huge plane just for the capacitors and other power components.
I have never seen such a thing, perhaps it exists? the layer would be added over the bottom layer, like an say a rectangle or square and only have
the vias for decoupling passing through it. sounds complicated but i cant see why not. its just another layer. and could be controlled just the same
as normal layers. so a say 6 layer board could have an additional localised two layers.
Actually, some chip designers make the BGA pinout the way, that it is easier for decoupling. But not everyone.
@@RobertFeranec Hi Robert, thanks for the response
Please tell us how to use polygon and power plan in two layers pcb
That's a little silly, "holes" appear when you mix via in pads and vias out of pads together, you can as well say that vias out of pads are creating hole if you try to put some in a design with all vias in pads, spacing remains the same no matter which way you choose, but be sure to choose one way, don't mix both. Sadly, no all BGA chips have enough spece to put capacitors, even if you choose cross pattern.
Hi Robert- how do you estimate the minimum number of signal layers you need in your stackup?
this is worth for an essay, I dont believe he can explain it very quickly, even though I need some help for that too, 4 layers vs 6 layers.
Regards from Czech Republic. Awesome video! I have one question. Whats your View Settings? You have all layers shown on bottom bar, and you view only one layer (with multiple net colors) then you click to another layer, and the view change only to another layer atc. I wonder how do you set it. Maybe, it would be a great idea for another video.
Dakujem. I am using Single Layer Mode (SHIFT + S, try press multiple times). For solid colors, go to System preferences -> PCB Editor -> Board Insight Color Overrides -> Solid
@@RobertFeranec Není zač, Thanks you for your answer.
Oh, you have changed the camera. No more wide angle, telephoto lens, nice portrait look. BTW IMX8 is a s****y SoC, so many power rails, so hot under load.
Thank you Alekcej. I a m very happy that some people are noticing my new camera setup :) PS: iMX8 - Thank you very much for pointing this out. From our previous experience with iMX6, we are careful about heat distribution, but I will be even more careful now.
Thanks for the helpful video again ! May i ask you one question ? Should all data lines be equal in lengths among themselves or in groups?
Thank you. PS: depends on interface, but usually groups are created the way, that the signals within group should have similar length.
About GND or Power plane between vias, a manufacturer suggested me to left out the ring of via on these layers, in order to maximize the space between two drilled holes. Anyone knows if it is a reliable practice? Thanks.
Does anyone have a reference design where it is shown how to fan out a 0.4mm pitch bga?
Can you please tell the name of the PCB fab which manufactures microvias for "a little bit more money"? Because all the fabs I know of the difference in price between thru-hole vias only and microvias is more like 2 times or more. If it not some kind of commercial secret, can you please tell the prices for both options? The fab I currently use makes 8 layer thru-hole only boards for ~220$ for 10 boards 10x10 cm with 3/3 mil traces and 0.2/0.35 mm vias. But they can't manufacture microvias, and all fabs I know of that do are massively more expensive.
Thank you Robert for a great Video ! ,
if uVIA is so much better why not use them for the whole bga Fanout ??
i think if you have 1 uVia or 100 uVias its still cost the same .
Also i have heard that uVia are slightly worse when it comes to reliability (This is what they tell us in our work place) is it true ??
Thank you Eyal. PS: For power pins I prefer to use through hole VIAs (bigger and better connection to power). We have not had problems with uVIAs (in the designs where we use them now), but I have seen some presentations especially about stacked VIAs and lower reliability. I think, we were talking about that a little bit also here: th-cam.com/video/FM3pRM0CxGw/w-d-xo.html
Maybe i skipped this part, but why via in pad is bad ? This is my preferred shortcut , and i don't like microvias since they cost more
I could not easily make space for the big capacitors under BGA.
@@RobertFeranec
This is why god invented 0201 :) but my BGA usually has 0.8mm pitch, so 0402 is used.
@@Kilohercas the big capacitors what I needed to fit there are 0402, the small one are 0201, but we needed higher value - that is why we needed the cross under the BGA.
If mixed, one characteristic of via in pad observed is solderability issues where the via consumes solder reducing amount of solder for the ball to pad connection. Also applies to other SMT connection types. If they are all via-in-pad variability is gone. Stencil apertures should be adjusted probably.
After applying the rules from the Xilinx document for 0.5mm pitch BGAs, Altium only places the outer two rows... Do you know what is causing this? (Its the iMX8M Nano)
i.MX8 is starting to get dated. I really hope nxp is working on some successor, maybe hexacore cortex-a78, that would be awesome.
Who knows what NXP will come up with. I have mixed feelings from their products and marketing. They have some super successful processors and then some failures and experiments. And if they have something successful, then they use the same name for next 10 processors which are totally different or not compatible with the successful one. It's then complete mess in their product lines.
Sir can you help with me snapdraogon apq8016 fanout in Altium?
I've been working on this project for past 2 weeks but I'm facing trouble while fanout.
It would be really great if I get a visual for that.
Thank you,
Pooja
Please go through the below link, maybe you got something useful.
designhelp.fedevel.com/forum/test/pcb-layout/10296-qualcomm-snapdragon-apq8016-fanout
vias must adhere to social distancing. :)
:)
Please subtitle I'm not understand :(:(
So real people design these types of boards? I though only Martians could do it since I still didn't manage to route a board that has one Arduino two resistor and one transistor
Subtitles required!
Robert, I have to ask: are you related to Lex Fridman ? There is an uncanny resemblance. Awesome video. Thank you sir
No, we are not related. But I googled him :)