Your BGA and You | PCB Layout
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- เผยแพร่เมื่อ 23 พ.ค. 2024
- If you're new to PCB Design, the concept of a BGA (or Ball Grid Array) may seem a little overly complicated. But, understanding BGAs helps open the door to mounting a lot of components in a single package. Tech Consultant Zach Peterson lays out everything you need to know to get started with BGAs.
0:00 Intro
1:12 What is a BGA?
2:30 Routing Traces into the Components
4:30 Constructing the Pads
5:58 Routing into the BGA
13:51 An Example BGA
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Design guide for BGA fanout and routing:
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One point you might want to cover is that chip manufacturers often allow violating impedance specs in the fanout area because there is simply not enough space for full-spec traces and spacing. It would be great if you make a video explaining how to create DRC rules which apply only to a certain portion of the PCB (like fanout regions of BGAs). I had to figure it out myself back in the day, but I'm certain many people will find it useful.
Sure they do, although that's not really a manufacturer "allowing" you to violate impedance in the fanout area. If that segment in the fanout area is electrically short then its impedance will be invisible to the I/O, and the signal will dominantly experience the transmission line impedance. In other words, the input impedance at an output pin on the BGA is dominantly just the transmission line impedance, not the impedance of the trace in the fanout section. Same idea going the other direction to an input on the BGA; if the fanout section is short enough then the incoming signal will only experience the load impedance on the BGA, not the fanout section impedance. We mentioned this in the input impedance videos, although not explicitly in the context of BGAs.
Your videos are edited with great clarity. Thank you for being so concise.
Thanks Zach! Waiting for your next video to learn more about BGA fanout techniques.
More to come!
Thanks Zach! Enjoyed your Webinar yesterday, thanks for that as well :)
Awesome, thank you!
Great video! The pattern of your shirt looks like the BGA footprint 😆
Good...!! this is a very interesting topic. Thank you so much!!
You are welcome!
5:30 I believe what you have described is an NSMD (Non solder mask defined) rather than SMD (Solder mask defined) pad. On SMD the solder mask goes on top of the pad and thus defines where the ball can stick. On contrary, with NSMD, solder mask is wider than the pad and thus the ball sticks to the whole pad. Note they are also called collapsing and non-collapsing pads.
Yes I did, I saw that during post, thanks for catching that!
@@Zachariah-Peterson Actually, what is your recommendation for fine pitch 0.4mm BGAs (WLCSP)? I see them often recommending to use SMD for such sizes due to VIP technology as otherwise the via would be larger than the pad itself and also for reduced chance of bridging.. 🤔
Brilliant , thank you.
Glad you enjoyed it
You are describing on about 5.10 the Soldermask defined pad. And it looks like the soldermask opening is bigger than the pad.
But I think, this is exactly the opposite, this should be smaller, not bigger
Can you clarify this please
Can you make a video on best practices for creating the BGA schematic component, i.e., how to choose how many gates you would create and how to use them in a schematic?
Sure we can do something like that, are you referring to some practices for creating the schematic symbols? There is a way to semi-automate this in Altium Designer with the component creation tools.
@@Zachariah-Peterson I’m referring to how you decide how many gates(blocks) you are going to divide the overall symbol into and decides which pins go to which gates. Then, if it’s not asking too much, can you show a FPBGA (or FPGA) used in a schematic, brought into a PCB design and show how you optimize the connections and transfer that back to the schematic?
@@mylon999 Oh I see what you're asking, that's a great idea I'll put it together this week!
So, I do have a couple of questions. First is related to the device soldering. In a direct dock board, the device gets directly soldered onto the PCB but what happens when you use a socket, like in the FT boards? Do the packages still have the solder balls on them? or there is some other way the connection is made?
Secondly, most fabricators are fine with via in pads even for coarse pitch devices, so why not use it with all BGAs regardless of the pitch? Also, since you are adding a trace with a via, won't it add inductance to the power planes?
Hey Waleed,
I've never used a socket like that for a large IC so I can't comment on all of those cases, however I know there are sockets with BGA footprints that are supposed to make those connections to the board. Some of these are test interposers, like for DDR memories, others are basically BGA-to-LGA or BGA-to-another-BGA adapters. And yes that's true about VIP, most fabricators can work with it but via filling for VIP can add costs, that's just something you would have to weigh when planning production. For the inductance it technically would add a little bit of spreading inductance but I don't think it would be very large.
@@Zachariah-Peterson Thanks for you comment!
@@Zachariah-Peterson Awesame, thank you for the videos!
For the inductance, we technically need higher inductance for the high-speed signal pins (we're coming from TQFN to BGA and TQFN regular L=1/1.5nH for a pin) and want to generate inductance on one of the L1/2/3/4 layers instead of the die consumes large area there. Do you have that kind of further detailed information you can share?
hello thanks fot the video , where can i find the BGA design guide video that you talked about comming soon ?
It looks like it might have been removed from the description, I added the link to the video description, please take a look
Great! Thanks
You're welcome!
please explain , f(w/h) with example. for select no of layers when choosing the BGA.
What I mean by that is the impedance of those traces depends on the value of the width to substrate thickness ratio, or (w/h). If you need to use thinner traces with high speed I/Os that need to reach in between two rows on a fine-pitch BGA, you can use a thinner substrate as this will require a thinner trace to hit the same impedance.
I am New to This I want to design a 289 pin BGA before I work on 4 layers only. Any suggestions I had a licence of Altium designer. what to refer for BGA design and If BGA ic is not present Then Is any video that suggested create custom Library for BGA package.
There are a few things you can do. First, you can use the IPC Compliant Footprint Generator wizard to create the component, this will give you the package without the requirement to copy and paste the pads by hand. To create the pin list is more complex, but I can create a video about it. For the layer count, just make sure you will have enough room to break out all the signals, with 4 layers on a SIG/GND/GND/SIG BGA that would leave 121 pins leftover that are probably all PWR and GND.
any video talked about via in pad fan out for BGA?
Yes, we just recently put up a new video and there is an older video on this topic. Here are the links:
th-cam.com/video/V4kGRnQGAjc/w-d-xo.html
th-cam.com/video/-L-0CkH3aEk/w-d-xo.html
How to fan out a BGA with a 0.4mm pitch and for example 64 Pins?
Is there any recommendation how to do it?
Depending on your fabricator capabilities you might need to do via-in-pad, it just depends on the solder ball pad sizes and the smallest features you can fabricate. You can do dog bone fanout if you can fabricate small enough vias; the diagonal pitch between pins would be 22.6 mils. In the HDI stuff that we've done we normally go with via-in-pad just because we need to have larger pad sizes for a high reliability product (Class III), in that arrangement you can still use larger pads as long as pad edge-to-pad edge spacing is large enough. So we would have a via plus annular ring that sets the pad size limit.
I requested someone internally create an example based on this, but it looks like I'll have to do it!
@@Zachariah-Peterson Thanks a lot
and thank you for all the knowledge that you share here on the youtube channel👍🏼
Since designs run at several 100s of MHz today, won't all PCB tracks or most, need impedance control and length matching?
Technically yes, it's going to be much better to just impedance match everything that has a fast digital signal (~20 ns or lower rise time) but not all interfaces have an impedance specification. For example, GPIOs and SPI/QSPI interfaces on modern chips can have very fast rise times, but they don't have an impedance specification on the bus, so you would have to determine what the output impedance is on those interfaces. This value varies from chip-to-chip.
You are showing a large BGA component @16:00, why not use smaller tracks and vias?
The vias are sized based on minimum annular ring targets in manufacturing, and a typical small drill size that can be used in mechanical drilling (10 mil diameter). For the traces, the traces shown in that part of the video are GND traces so the width is not extremely important other than for lowest impedance return paths.
Thank you Zach!! I wanted to know why do we need a separate ground plane for controlled impedance trace?
Hi Jagan, you just need to have ground near the trace to set the impedance to the required value. In this case where you are routing multiple impedance controlled interfaces on multiple layers, you might need to have multiple ground layers. That's the easiest way to shield those interfaces from each other and provide the controlled impedance value you need.
With all those grouped ground pins, why not just connect them with a mini-plane? If the problem is that is makes soldering unreliable, why not at least cross-connect them? (Essentially a ground plane with the thermal relief around the pins.)
Hi Jim, They are connected to ground on L2 (you can see the layers in the View Configuration panel on the right side). Same thing goes for the different groups of power pins, they are connected to different power segments on L3. For the ground pins, you could connect them together with a big ground polygon, but for this board there was already a ground plane on the next layer, so it wasn't really necessary to also put a bunch of grounded copper pour on the surface layer.
@@Zachariah-Peterson So are you saying that your default is to NOT do a ground pour unless you have to, rather than doing one unless it would cause problems? (I'm assuming the rule of thumb that you should have a via for every pad, and that this would be more than enough to keep the pour well-connected to the plane below.) Is this in any way related to copper balance, or to some other rule that I can't even think of yet?
@@jimjjewett No that's not what I'm saying, I mean that the ground plane on the next layer in my example provides the same function as the ground pour you're referring to: it links together all those GND pins that are clustered together beneath the BGA. Same idea with power, you can do it with a large rail. I'm saying you just don't need to always do it with GND pour on the surface layer beneath a BGA. You probably don't need to do this with additional pour as long as you located the GND planes properly.
As far as doing GND pour if you have to, when you have a big set of GND pins like that and they are connected with a correctly located GND layer, you don't really have to place the GND on the surface below the BGA. I suppose you can do it if you want, but will it create any additional benefit? If for some reason, you decided NOT to put a GND pour on the next layer, then you might need one on the surface to provide some level of shielding and to tie all those pins together as you mentioned. However, you would still need to connect those pins somewhere else, ideally through another internal layer. What I'm dealing with in these systems normally is at least one high speed interface that needs to be shielded from a set of moderate/low speed IOs, so I put the GND between on an intervening layer to separate them and to tie all the GND pins together. It's just the simplest way to do it from multiple perspectives.
I think I get what you're hinting at though; those GND pins might not be all grouped together like my example component, so you might need some additional GND to provide some shielding, is that correct?
@@Zachariah-Peterson I'm not hinting; just trying to figure out if this is a huge hole in my understanding. My thought was that thicker traces, at least for power and ground, are almost always better, and planes better still -- even if you don't need them. Assuming that there is a good ground plane right underneath means you don't *need* a pour between the pins, but having one should add some reliability/yield through redundant vias, and should reduce ground ripple both because pins will not all be simultaneously active (so the current can be split among multiple vias) and because the pour itself will have some capacitance against the main ground plane. (Only to the extent that they are at different levels, but ... isn't a short deviation from the expected level the whole point behind most capacitors?)
@@jimjjewett No I don't think you have a huge hole in your understanding. This is an interesting point and it relates to the copper pour discussion I had with Bogatin on the OnTrack podacst, so I want to look into it more. For a high reliability design I would agree with you in the case of redundancy, but you might still cut it up with interleaving vias. If you're doing something like an OpenVPX/VITA backplane which has stringent manufacturing reliability standards, those clearances are larger than the standard IPC-compliant device and you might not be able to fit GND under a fine pitch BGA, so you would rely on additional planes if you wanted redundancy. And yeah the pour has some capacitance to the main GND plane, but you've basically shorted those conductors with vias so that they are (ideally) always at the same potential and it would never source or sink charge. Obviously that doesn't happen in reality, if any signal capacitively couples onto that pour instead of GND plane it will now have an easy path back to the GND plane, not a bad thing if you think about this in terms of shielding. I just don't know for sure there is a benefit in terms of ripple reduction. I'm not saying it creates MORE ripple or that it will hurt anything else in terms of signal integrity, even if the pour spans around controlled impedance connections that might interleave between GND pins since those connections are very short electrically. But if you have GND pour over a GND plane I don't think it's going to provide additional charge storage with respect to power because the vias short the pour and the plane. TBH I don't know how the capacitance w.r.t. another plane for those kinds of stacked structures changes as you add more shorted pour regions above them, maybe it does and maybe it doesn't, I've never seen any measurements of this so I don't want to say you're wrong or anything like that. If you had a power plane interleaved between the pour and the GND plane then you would certainly get some additional capacitance in the PDN. That's how folks like Hartley and Ritchey have stated they use copper fill.
Is invention of high pitch BGAs really necessary and worth it?
Yes necessary and worth it when high number of features are needed in very small spaces.
@@Zachariah-Peterson I am trying to learn Altium and have a confusion. When we create PCB footprint, what extra layers do we add ourself? 3D body, assembly drawing, courtyard and any other? When I use the wizards inside Altium, they create these mechanical layers but only as single layers. However, when I look around on internet, I see that people create layer pairs for these things and not single layers. It is all very confusing.
you just skipped a crucial point about defining the size of the pad. Many manufacturers like XILINX do not provide any recommendation for the land pattern in their datasheets. What to do then? I think you should cover that. There are calculators, IPC calculators, simulations, etc.
Hi carlos, I just recorded a video on this today, it will go up in a few weeks. Short answer is: there is a table in the IPC-7351B standards that provides pad size allowances for given standardized ball diameters. You can see the table here: i.stack[dot]imgur[dot]com/fS6WA.png