"Buildings have walls and halls, people walk in the halls. PCB's have traces and spaces, the energy travels in the spaces." Quote as I remember it from Ralph Morrison. Nice presentation!
I jumped into PCB design with no EE education. I learned a few of these tricks from my mistakes and realizing why things were not working as expected. Some of these things are also new to me, glad I watched 👍
Omg Phil has a FACE!!!!! Love his content on his channel, and I now know why he's so knowledgable, and great at working in Altium designer (and has it to begin with)! Please Phil, keep making as much content across all channels as you can as it's always amazing
Wouldn't you want to place the decouppling capacitor closest to the IC and THEN place the VIAs (so your arrangement would look as following: VIA -> capacitor pad -> IC power pin)? Since with your arrangement, in the instant of the IC requirimg more current the direction of flow of current will be capacitor -> VIA -> IC and ... -> VIA -> IC pad and after that, when charge will be moved back to the capacitor the direction of flow of current will be ... -> VIA -> IC and ... -> VIA -> capacitor. This would result in a much bigger change of the electromagnetic field, compared to having a uniform direction of flow of current from the "VIA -> capacitor -> IC"-arrangement. Edit: please correct me if I'm wrong
I was about to mention that, the way you do is a preferred one for me, makes more sense having VIA -> CAP -> IC that give the real purpose of having decoupling capacitors, otherwise, the capacitor is just an expectator.
You are not wrong this is preferable but the importance can also be overstated in my opinion. In FPGA designs all the decoupling is mostly placed on the bottom side so the BGA pin sees a power plane first.
@@melvinegberts2347 Yes, of course. It's just, if you can do it the better way why do it the less perfect way :) It's the same with decouppling as a whole. Many things would probably still work (maybe not as good) but if you can you should add decoupling
What a great way to explain having reference planes directly underneath your signals. Great video and haven’t thought about why we wanted to stay away for voids due the the magnetic fields spreading out and needing a reference plane.
Hi Phil, Glad to see you here. I'd like to point out 09:55 where you placed vias between MCU and Capacitor. Robert Feranec discouraged this practice saying the capacitor will have not help much cuz it is out of the way. He recommended Power trace should pass through the pad of capacitor. See his video series where he created magic wand Board. Can you explain what's better to do? Thanks
In Phil's example, placing the vias between the cap and device is usually fine because of the frequencies generally associated with a MCU. In this case the main goal is to decouple the device from the PDN while it is switching by supplying the demand for energy quickly enough to limit voltage transients from forming on the plane. Bypass cap placement (as used in analog circuitry) is more about filtering noise that already exists on the planes from getting into the device, potentially being amplified. In that case you absolutely want to have the cap between the device and the vias. PDN capacitor placement decisions often come down to digital vs. analog concerns and the ability to route a low impedance path at the frequency of interest. General rule of thumb is the smaller the capacitor value, the less layout induced parasitic inductance can be tolerated in it's (both forward and return) path. This is why the smallest value caps are always placed closest to the load and load return pins. The discussion of placement and routing should include the value of the cap, and this one is most likely in the .1uF range, not 1pF.
Correct! The impedance to the capacitor should be small. Because the vias have cosiderable self-inductance, it is often better to put the caps first and then the vias to the plane.
Agree. Was literally pondering this, and decided on the same answer as you. The whole point of the capacitor is having a small energy source, but with an ultra-low impedance path to the pin. The routing to the MCU pin should be prioritized for the cap, not the power plane. After all, a slighty longer path to the the power plane might only add (say) +1% total source impedance in that case. However, doubling the distance to the cap (pin-via-cap vs pin-cap-via) might double the effective impedance to that capacitor, reducing it's effectiveness.
Hey, As is always the case with PCB design: it depends. Rick Hartley suggests various methods depending on the scenario. The cap connection method and via placement depends on the stack-up, arrangement of power planes, if there is routed power or not, and more. For routed power, decap connections straight into IC pins, however the rail vias going to the cap need to be spaced far apart to raise inductance of these connections (for 'true' decoupling). For widely spaced planes the method I showed in this video is the preferred one (I showed this, as a preferred 'beginner' 4-layer stack-up is SIG-GND-PWR-SIG with a thick core separating GND and PWR). And finally, for closely spaced power planes, the decoupling cap position and their attachment to the planes is largely irrelevant as long as they are 'close enough' (within radius defined by IC rise time). There is much more to this subject and I'll be mKing a video on this. Happy to share some of the Rick Hartley slides/information with you for further details. Also, check out Dr Howard Johnson's article "Bypass Capacitor Sequencing" which shows preference to the method shown in this video.
It is mostly ok as long as the capacitor is close enough, though I personally tend to make the through-pad routing whenever possible just because it feels better.
Good stuff. I'd be interested to hear your thoughts on when and how to do via stitching down to ground planes for fast or noise sensitive outer signals, copper pour etc.
I agree. I've managed to create a dozen or so very almost trivial PCBs that work, but as I look at more ambitious projects I'd like to be able to tell where I need to study new factors.
It depends. 2 layer boards often do not carry critical signals. In that case you don't have to care. But if you have got sensitive signals on your 2 layer PCB, I highly recommend to obey this rule. When you don't have enough space, maybe it is time to consider a 4 layer board.
Despite being an Aussie and using metric my entire life I've used imperial 0.1" scale literally since the first days of Protel. My brain just can't work back to using mm for pcb stuff :(
I think you must clarify how to properly calculate THT holes and VIA's. For a PCB manufacturer, the annular ring size is not equal to( PAD size - drill size) / 2. Instead, manufacturers use a larger drill and the the final hole (the specified hole size in your drill data) size is achieved after plating. because of this, you must always design VIA's and THT PAD's with an annular ring larger than the minimum requirement. The rule I apply: (PAD size - drill size +0.1mm) / 2 must be larger or equal than the manufacturers minimum annular ring requirement. If in doubt, your PCB manufacturer can specify the requirements.
Some DDR4 routing guidelines say that if half of the trace is over GND reference for via voids, it's should be okay. Not the thing to aim for, but keep in back po ket for when designs get super dense
Lack of copper balance on inner layers is also one of them. You cant expect to have the same prepreg thickness on a layer with 10% copper as on a layer with 80% on the same PCB. Designers need to learn that good copper balance of at least 80% is king.
Hey Phil, Great video. Just a couple of comments you might consider reading: 1. Please note that annular ring - by definition - is calculated from the DRILL SIZE, and NOT the finished hole size that you specify as the VIA hole size in Altium. Your calculation in the video is therefore... wrong. A 0.5mm dia finished hole size VIA is drilled with 0.55 - 0.6 mm dia drillbit. That is what you have to subtract from 0.9 and then divide the result by 2 to get the real annular ring size. Similarly, VIA aspect ratio that you talk about is NOT calculated from the finished hole size, but the drill size, what you cannot actually see in Altium, unfortunately! Also note that over 0.45-0.5mm of finished hole size, vertical interconnects are often considered through-hole pads rather than vias by the fabricator. Different plating tolerance figures apply. 2. The purpose of decoupling caps - besides acting as local energy storage, as you said - is what their name suggests, decoupling high frequency noise by providing a low impedance path for disturbances, and close the circuit as close as possible to the switching noise source, that is, the power pins of the IC. For this reason, the most widely accepted placement of the plane VIAs is not between the cap and the chip, but on the other side of the cap. Other than these, all your words are gold, and the presentation is excellent. Thank you for sharing. 😊
Your technical observation is very good except the decoupling capacitor term should be closer to analog signal attenuator / peak voltage attenuator capacitor.
@@saludosbuenosamigos Hey mate, not sure what you mean by "analog signal attenuator / peak voltage attenuator capacitor" here, but in this given example (and most likely in any other) the only thing that the pwr decoupling cap must be close to is the power pins of the IC. 🙂
Thank you again @Philip Salmony for sharing your experience! I'm a complete novice with electronics, but I'd like to get something clarified. You have mentioned inductance, capacitance, electronic fields, trace widths, trace length, vias, de-coupling, etc ... (all as a rule of thumb of course - all of which are very valuable!).... A very simple question regarding all of this, if I may? If all signals flowing through the tracks are < 1MHz, power is < 5V and < 1A with 2A peaks, how much should I be worried about your PCB layout concerns? (IC-local capacitors considered)?
For power decoupling capacitors, it's not about the signals on the wires, it's about how quickly the signals change. There's another valuable rule of thumb: gif the rise time of your signal is t, then your system must be designed for frequency f = 0.35/t. For 1 ns rise time, that's 350 MHz. You can have a 1 Hz square wave, but if that square wave has a rise time from 0 to hero in 1 ns, then the equivalent current it takes to charge the capacitance of that wire from 0 to 5V in 1 ns is quite large. If there's no decoupling capacitors, then that current must come from the capacitors of the power supply (may be 1m away through a cable), and that sure as shit ain't happening. Now the question is: how sensitive is the switching component (or a neighbouring one) to the supply voltage dipping, or to the signal NOT rising in 1 ps because there wasn't enough electrons available in local storage? If the chip doesn't care, and the thing receiving said signal doesn't care? Then all is right in the world. If they do? Now you have a device that resets 5% of the times that signal changes. Modern chips usually limit the rise times, when driving external IO. That's also the reason you may have seen drive strength options for IO-s in modern MCU-s. The other thing is the processor or logic in the chip itself. The clock signal running a modern MCU is almost certainly in the tens of MHz, and with every clock cycle, potentially millions of transistors change state. During that state change is essentially the only time CMOS logic draws any current: both to charge the signal capacitances inside the chip, and maybe also as shoot-through current. These are the real reason decoupling caps are needed: those transitions are quick, and if the supply can't keep up, your logic may end up not logic-ing correctly because a certain logic gate didn't get enough juice to update it's output in time for the next one to react in time...
Since the donationware software from Saturn is used throughout a lot of this video, it would have been nice to have a link to them or mentioned that some sort of commercial license was paid since this is a commercial company using it. Beyond that point, this is a great video.
a real design flaw is to put a 48 volt backlight power trace next to the data trace on the ribbon cable to the display where it could arc over and blow the cpu. on certain macbooks there was a flaw where the 48 volt backlight trace was next to the data trace that goes to the cpu so if the backlight circuit was to arc over it would fry the cpu. having the decoupling caps close to the power rails makes better security sense if you intend to pot the chip you can include the decoupling caps in the blob of plastic so it would not be so easy for a hacker to glitch the device and dump the firmware. the apple air tag was hacked because apple placed the decoupling caps far enough away from the chips that someone was able to solder onto the the caps and glitch the device and bypass the built in anti dumping of the firmware.
I imagine even if you do that, people can xray the package and then drill into it with a stop until the potted in capacitor pops, and do the glitching attack then. I don't think it's a product security strategy to rely on; you really need good brownout.
@@SianaGearz the drilling into the die and destroying something on the die is exactly how the security on a video game console (i think playstation) was done. the maker integrated some chip into another chip to make it impossible to get homebrew or linux on the console.
Very inspiring and thoughtful video, congrats. However, there's something I just don't get it: in 4:10 you've claimed that for high impedance signals one must reduce traces width. I believe you, but there is any chance that you point me out to the theory behind such statement? My first thoughts are on impedance matching fact, however I want to be sure, and if I'm wrong, to understand your claim Thank you in advanced! 😀
A thinner trace has a higher resistance, and resistance maps directly to impedance at all frequencies. It's not a "high impedance signal", it's a high impedance input. A signal doesn't have an impedance, impedance is an attribute of a circuit component. For the sake of intuition it is quite useful to think of electrons as compressed air in a rigid system of pipes. Voltage is directly analogous to pressure in such a system, current is analogous to the mass flow rate of air, power is still power. Imagine you're designing an air compressor. If you use a big tank, you need a big motor and pump if you want to be able to fill it up to working pressure as quickly as a smaller tank with an equally smaller motor. To fill a larger tank to the same pressure as a smaller tank in the same amount of time, you need a higher mass flow rate out of your pump. The motor and pump are analogous to the source of your signal. If your signal source is very small, and only delivers a small amount of current, you want to use a smaller tank (i.e. a thinner trace) to store that current and build up a voltage you can measure. Alternatively, think of every wire as being connected with a capacitor to ground. This is actually how we model wires in sensitive applications, using a "transmission line" model. A thinner trace has a smaller capacitance to ground simply because it has a smaller area. The impedance of a capacitor is inversely proportional to the frequency of the signal, so a thinner trace can carry higher-frequency signals with less power loss than a thicker one.
It's directly related to the previous section about track spacing. Greater spacing reduces coupling between traces. A narrow trace will allow greater spacing while using the same route.
I was about to say now try to route the traces after decoupling capacitors are placed, then i watched the rest of the video. But if you are using cases bigger than 0402, it is impossible to fit as close as in this video.
Hi, thanks for the nice video. At 9:50 you place the vias to the power & ground plane between your de-coupling capacitor and the chip. Wouldn't it be better to place the capacitor between the chip and the vias to filter out the most amount of transients before drawing from the plane capacitance? Thanks
Thanks! For small annular rings we need better tolerances/alignments for the drill hole. The drill hole will never be perfectly central to the via, so a smaller annular rings requires a more precise drill.
Also watch out for too large of an annular ring. Larger vias aren't always better, In the QFP design Phil was showing too large vias will most likely unnecessarily swiss-cheese the planes by the time routing is complete. General rule of thumb is to use a 5 mil annular ring unless ruggedized/class III then use 6 or 7.
Decoupling caps should be as close as possible to the IC but the vias to the power/ground planes should not be placed between the cap and IC. To minimize noise you want the majority of the required energy coming from the cap and not the power rails. So have a thick trace from the cap to the IC to allow for short bursts of energy. But then "charge" the caps using a smaller trace to a via adjacent to the cap but opposite from the IC. This results is lower surge currents to/from the power rails and helps reduce overall noise. In general, keep the trace between the cap and IC twice the width as the trace between the via and cap.
I have a big doubt, that it's a good idea to place vias between decoupling capacitor and IC. I think it's better to swap the capacitor and vias placing.
Hello, great video. I'm new to Altium and I have a question: When designing my pcb, I imported my components and I try to connect my pins or rather the pads of a component between them. When I try to connect 2 pads together, I manage to make my trace start from the center of my 1st pad, but I cannot connect this trace to a 2nd pad. The trace avoids the pad. Do you know where the problem comes from and how to solve it? Thank you in advance for your precious support 😊 Cordial greetings. 1: Do you know where the problem comes from? 2: Do you know how to solve it? Thank you in advance for your precious support 😊. Cordially.
Decoupling capacitors should be placed between vias and pins. Because the current choose the shortest track and the lower impedance. If the via is placed between the decoupling capacitor and the pin, the contribution of decoupling capacitor will be significantly lower.
5:20 Length of the conductor is only 10mm(!) so of course those amps looked crazy high... Remember also to take consider the length of the conductor when calculating the proper width for your traces.
Good video. I just have a doubt about putting vias on decoupling capacitors between the IC pin and the capacitor pad. Usually I put the via before the capacitor pad.
It depends on whether you have closely spaced power and ground planes. In case you have a multilayer board with ground and power layers directly under the IC with few mils separation then it is as you stated, IC pad => via => cap pad. In cases such as 4-layer or 2-layer boards, it has to be via/trace => cap pad => IC pad. The goal is to have a local energy reserve with minimal inductance for the power pads.
@@km-electronics1 One of the software engineers I work with found this video and linked it to me asking the exact same question. I kind of struggled to answer. Is this video saying that placing the vias between the cap and the IC reduces inductance when compared to placing the cap between the via and IC? Or is it saying that it reduces the inductance to have via, cap and IC pins as close as possible? The interpretation of my software engineer friend was the former example. I’ve always put a preference on IC > cap > via, or having via in pad (other requirements allow me to do this), and only if needed I’ll do IC > via > cap, but only on low speed signals and large capacitor values. How does IC > cap > via compare to via in pad (via in the capacitors pads)?
In Phil's example, placing the vias between the cap and device is usually fine because of the frequencies generally associated with a MCU. In this case the main goal is to decouple the device from the PDN while it is switching by supplying the demand for energy quickly enough to limit voltage transients from forming on the plane. Bypass cap placement (as used in analog circuitry) is more about filtering noise that already exists on the planes from getting into the device, potentially being amplified. In that case you absolutely want to have the cap between the device and the vias. PDN capacitor placement decisions often come down to digital vs. analog concerns and the ability to route a low impedance path at the frequency of interest. General rule of thumb is the smaller the capacitor value, the less layout induced parasitic inductance can be tolerated in it's (both forward and return) path. This is why the smallest value caps are always placed closest to the load and load return pins. The discussion of placement and routing should include the value of the cap, and this one is most likely in the .1uF range, not 1pF.
Hi as you said we have to good spacing between traces it's a question for me if i have good space between my traces but i fill this space with ground plane can make crosstalk or noise?????
Crosstalk will always occur between two traces, it’s just a matter of whether or not you notice the crosstalk or whether it’s actually measurable. Take a look at this other video (th-cam.com/video/K1ob42Pv74Y/w-d-xo.html), it shows different situations where adding copper between two traces can increase noise in some cases, depending on whether the copper is floating or terminated to the trace’s impedance. That video looks at guard traces, but filling with copper between two traces is very similar to a guard trace, it is usually just much wider. The increase or decrease in crosstalk also depends on whether you are looking at striplines or microstrips.
You forgot to mention, that people should stop using signal, gnd or power plane, gnd or power plane, signal stackup. It leads to all sorts of signal integrity and EMI problems. Signal and routed power, gnd plane, gnd plane, signal and routed power should used instead.
At th-cam.com/video/D0X76Kbf8fQ/w-d-xo.html are you really saying that a narrower trace is inherently less subject to crosstalk, or only that narrower is OK, so it is better to use that extra space to increase separation from the nearest neighbor?
Hi Phil Amazing content as usual! Thank you for this. I have the same comment as last video at 9:54 regarding the positioning of your de-coupling vias in relation to the IC pads and the de-coupling cap. I realize you probably had this video made and edited and ready to go but I wanted to re-iterate that the ordering is incorrect.
Hi again, Sorry for not having gotten back to your comment on the last video. I attended a Rick Hartley seminar and he stated that this is the preferred placement for vias to minimise both inductance to (widely spaced) planes and decoupling cap (happy to share the relevant slide with you). Now, for routed power this is slightly different and it is preferentially to do GND via -> cap pad -> IC, as you state. In an ideal world, one would have GND(/PWR) vias directly next to the both sides of the MCU pads and the cap.
@@PhilsLab Can you share that slide? I was discussing with my team - and everyone agreed they had been taught vias outside the decoupling cap. Interested to see the details on this recommendation.
@@jerrybeckmann1323 Jerry, I don't have that referenced slide, but check out Howard Johnson's article "Bypass Capacitor Sequencing." He favors the approach with vias between the IC and the decoupling capacitor to create a lower impedance path.
Interesting. I had learned that the via was a larger inductance than the trace, so the capacitor was creating a mini power plane to handle the local ups and downs from the larger power plane. Much more of keeping the noise of the power supply reaching the pin. I’ll have to do some simulations to see the impact here. Good read :)
Nope, this is fine. This is not analog nor PAM4, just an MCU. Some of the highest speed devices come in BGA packages where the vias are almost always between the cap and the device. Granted the high-frequency caps are moving to being on chip now, but the .1uF mid-range decoupling is perfectly fine connected as Phil shows, and if 10uF or above does not need to be near the device vias at all.
@@ekenedilichukwuekeh4647 The point of decoupling is to limit transients from forming on the plane, the point of bypassing is to remove noise. Priority of one vs the other, and the value of the cap, helps us make the decision on how to connect.
i'm pretty sure that the last one, at least as demonstrated, should not be even considered to be a mistake, not one little bit. Just the solder joint on the chip the trace goes from is probably an order of magnitude more of a disruption, than the tiny bit of opening of the round plane below a tiny fraction of the length of the track.
it's wrong your distance between chip and your via and cap 3.3v is very closet and while a person that want solder a chip have a problem or in repairing or testing
![ลองสุ่มไอโฟน 990 โกงมั้ย? [ โกงมั้ยครับ ep.101 ] | DOM](http://i.ytimg.com/vi/bfsWe0j492k/mqdefault.jpg)
"Buildings have walls and halls, people walk in the halls. PCB's have traces and spaces, the energy travels in the spaces." Quote as I remember it from Ralph Morrison. Nice presentation!
I jumped into PCB design with no EE education. I learned a few of these tricks from my mistakes and realizing why things were not working as expected. Some of these things are also new to me, glad I watched 👍
We want more content with Phil ! Thank you for the advice!
Thanks, Alexandros!
Omg Phil has a FACE!!!!! Love his content on his channel, and I now know why he's so knowledgable, and great at working in Altium designer (and has it to begin with)!
Please Phil, keep making as much content across all channels as you can as it's always amazing
Wouldn't you want to place the decouppling capacitor closest to the IC and THEN place the VIAs (so your arrangement would look as following: VIA -> capacitor pad -> IC power pin)? Since with your arrangement, in the instant of the IC requirimg more current the direction of flow of current will be capacitor -> VIA -> IC and ... -> VIA -> IC pad and after that, when charge will be moved back to the capacitor the direction of flow of current will be ... -> VIA -> IC and ... -> VIA -> capacitor. This would result in a much bigger change of the electromagnetic field, compared to having a uniform direction of flow of current from the "VIA -> capacitor -> IC"-arrangement.
Edit: please correct me if I'm wrong
You are not wrong.
I was about to mention that, the way you do is a preferred one for me, makes more sense having VIA -> CAP -> IC that give the real purpose of having decoupling capacitors, otherwise, the capacitor is just an expectator.
@@TheBENHEC Not just for you...
You are not wrong this is preferable but the importance can also be overstated in my opinion.
In FPGA designs all the decoupling is mostly placed on the bottom side so the BGA pin sees a power plane first.
@@melvinegberts2347 Yes, of course. It's just, if you can do it the better way why do it the less perfect way :)
It's the same with decouppling as a whole. Many things would probably still work (maybe not as good) but if you can you should add decoupling
Very clear, informative and straightforward, I like to see this guy more often.
Glad you enjoyed it!
Good to see Philip doing these. Definitely get him to do more.
Thank you Altium team , for every time sharing such technical knowledge. 🙏
Our pleasure!
What a great way to explain having reference planes directly underneath your signals. Great video and haven’t thought about why we wanted to stay away for voids due the the magnetic fields spreading out and needing a reference plane.
Hi Phil, Glad to see you here.
I'd like to point out 09:55 where you placed vias between MCU and Capacitor.
Robert Feranec discouraged this practice saying the capacitor will have not help much cuz it is out of the way.
He recommended Power trace should pass through the pad of capacitor.
See his video series where he created magic wand Board.
Can you explain what's better to do?
Thanks
In Phil's example, placing the vias between the cap and device is usually fine because of the frequencies generally associated with a MCU. In this case the main goal is to decouple the device from the PDN while it is switching by supplying the demand for energy quickly enough to limit voltage transients from forming on the plane. Bypass cap placement (as used in analog circuitry) is more about filtering noise that already exists on the planes from getting into the device, potentially being amplified. In that case you absolutely want to have the cap between the device and the vias. PDN capacitor placement decisions often come down to digital vs. analog concerns and the ability to route a low impedance path at the frequency of interest. General rule of thumb is the smaller the capacitor value, the less layout induced parasitic inductance can be tolerated in it's (both forward and return) path. This is why the smallest value caps are always placed closest to the load and load return pins. The discussion of placement and routing should include the value of the cap, and this one is most likely in the .1uF range, not 1pF.
Correct! The impedance to the capacitor should be small. Because the vias have cosiderable self-inductance, it is often better to put the caps first and then the vias to the plane.
Agree. Was literally pondering this, and decided on the same answer as you. The whole point of the capacitor is having a small energy source, but with an ultra-low impedance path to the pin. The routing to the MCU pin should be prioritized for the cap, not the power plane. After all, a slighty longer path to the the power plane might only add (say) +1% total source impedance in that case. However, doubling the distance to the cap (pin-via-cap vs pin-cap-via) might double the effective impedance to that capacitor, reducing it's effectiveness.
Hey, As is always the case with PCB design: it depends. Rick Hartley suggests various methods depending on the scenario. The cap connection method and via placement depends on the stack-up, arrangement of power planes, if there is routed power or not, and more. For routed power, decap connections straight into IC pins, however the rail vias going to the cap need to be spaced far apart to raise inductance of these connections (for 'true' decoupling). For widely spaced planes the method I showed in this video is the preferred one (I showed this, as a preferred 'beginner' 4-layer stack-up is SIG-GND-PWR-SIG with a thick core separating GND and PWR). And finally, for closely spaced power planes, the decoupling cap position and their attachment to the planes is largely irrelevant as long as they are 'close enough' (within radius defined by IC rise time). There is much more to this subject and I'll be mKing a video on this. Happy to share some of the Rick Hartley slides/information with you for further details.
Also, check out Dr Howard Johnson's article "Bypass Capacitor Sequencing" which shows preference to the method shown in this video.
It is mostly ok as long as the capacitor is close enough, though I personally tend to make the through-pad routing whenever possible just because it feels better.
Good stuff. I'd be interested to hear your thoughts on when and how to do via stitching down to ground planes for fast or noise sensitive outer signals, copper pour etc.
Thanks, Rob - that's a good idea for a video!
I agree. I've managed to create a dozen or so very almost trivial PCBs that work, but as I look at more ambitious projects I'd like to be able to tell where I need to study new factors.
For the first rule of thumb, what happens when the board is a 2 layer board and the dielectric thickness is much greater?
It depends. 2 layer boards often do not carry critical signals. In that case you don't have to care. But if you have got sensitive signals on your 2 layer PCB, I highly recommend to obey this rule. When you don't have enough space, maybe it is time to consider a 4 layer board.
Question for power traces when there is a lot space: should those traces be as big as space permits?
Despite being an Aussie and using metric my entire life I've used imperial 0.1" scale literally since the first days of Protel. My brain just can't work back to using mm for pcb stuff :(
The future is metric 😅
I think you must clarify how to properly calculate THT holes and VIA's. For a PCB manufacturer, the annular ring size is not equal to( PAD size - drill size) / 2. Instead, manufacturers use a larger drill and the the final hole (the specified hole size in your drill data) size is achieved after plating. because of this, you must always design VIA's and THT PAD's with an annular ring larger than the minimum requirement. The rule I apply: (PAD size - drill size +0.1mm) / 2 must be larger or equal than the manufacturers minimum annular ring requirement. If in doubt, your PCB manufacturer can specify the requirements.
Fantastic video!
Excellent! I'm passing this to my students!
Thanks for sharing!
It is nice to see phil here on Altium
Thanks, Ahmed :)
@@PhilsLab thank you i started using kicad after your stm32 pcb designs.
Great stuff! I love that you clearly edit your videos by the audio waveform, not the pixels 😂😂
Hey it's Phil from Phils Lab TH-cam channel. He's got a lot of good videos on PCB design; mostly based around DSP projects. Good videos here as well.
Some DDR4 routing guidelines say that if half of the trace is over GND reference for via voids, it's should be okay. Not the thing to aim for, but keep in back po ket for when designs get super dense
Yes, in dense designs routing over partial voids will be very difficult - especially for a through-via board.
How much does it cost on average to look over a board and give feedback/advice on it.
Really helpful general advice here, even when using a different tool. Thank you for sharing Phil.
Lack of copper balance on inner layers is also one of them. You cant expect to have the same prepreg thickness on a layer with 10% copper as on a layer with 80% on the same PCB. Designers need to learn that good copper balance of at least 80% is king.
Could you explain this more for the newbies?
Still working as of today, ty!
Nice to see you here, Phil :)
Thank you. Please keep making these
Thanks for watching!
Hey Phil, Great video. Just a couple of comments you might consider reading:
1. Please note that annular ring - by definition - is calculated from the DRILL SIZE, and NOT the finished hole size that you specify as the VIA hole size in Altium. Your calculation in the video is therefore... wrong.
A 0.5mm dia finished hole size VIA is drilled with 0.55 - 0.6 mm dia drillbit. That is what you have to subtract from 0.9 and then divide the result by 2 to get the real annular ring size.
Similarly, VIA aspect ratio that you talk about is NOT calculated from the finished hole size, but the drill size, what you cannot actually see in Altium, unfortunately!
Also note that over 0.45-0.5mm of finished hole size, vertical interconnects are often considered through-hole pads rather than vias by the fabricator. Different plating tolerance figures apply.
2. The purpose of decoupling caps - besides acting as local energy storage, as you said - is what their name suggests, decoupling high frequency noise by providing a low impedance path for disturbances, and close the circuit as close as possible to the switching noise source, that is, the power pins of the IC. For this reason, the most widely accepted placement of the plane VIAs is not between the cap and the chip, but on the other side of the cap.
Other than these, all your words are gold, and the presentation is excellent. Thank you for sharing. 😊
Your technical observation is very good except the decoupling capacitor term should be closer to analog signal attenuator / peak voltage attenuator capacitor.
@@saludosbuenosamigos Hey mate, not sure what you mean by "analog signal attenuator / peak voltage attenuator capacitor" here, but in this given example (and most likely in any other) the only thing that the pwr decoupling cap must be close to is the power pins of the IC. 🙂
It's Phil!!! ❤❤🔥
Hi Minol :)
I learnt many things from your video. Thank you !
Thanks, Sanjay!
Glad it was helpful!
Thank you again @Philip Salmony for sharing your experience! I'm a complete novice with electronics, but I'd like to get something clarified. You have mentioned inductance, capacitance, electronic fields, trace widths, trace length, vias, de-coupling, etc ... (all as a rule of thumb of course - all of which are very valuable!)....
A very simple question regarding all of this, if I may? If all signals flowing through the tracks are < 1MHz, power is < 5V and < 1A with 2A peaks, how much should I be worried about your PCB layout concerns? (IC-local capacitors considered)?
For power decoupling capacitors, it's not about the signals on the wires, it's about how quickly the signals change. There's another valuable rule of thumb: gif the rise time of your signal is t, then your system must be designed for frequency f = 0.35/t. For 1 ns rise time, that's 350 MHz. You can have a 1 Hz square wave, but if that square wave has a rise time from 0 to hero in 1 ns, then the equivalent current it takes to charge the capacitance of that wire from 0 to 5V in 1 ns is quite large. If there's no decoupling capacitors, then that current must come from the capacitors of the power supply (may be 1m away through a cable), and that sure as shit ain't happening.
Now the question is: how sensitive is the switching component (or a neighbouring one) to the supply voltage dipping, or to the signal NOT rising in 1 ps because there wasn't enough electrons available in local storage? If the chip doesn't care, and the thing receiving said signal doesn't care? Then all is right in the world. If they do? Now you have a device that resets 5% of the times that signal changes.
Modern chips usually limit the rise times, when driving external IO. That's also the reason you may have seen drive strength options for IO-s in modern MCU-s.
The other thing is the processor or logic in the chip itself. The clock signal running a modern MCU is almost certainly in the tens of MHz, and with every clock cycle, potentially millions of transistors change state. During that state change is essentially the only time CMOS logic draws any current: both to charge the signal capacitances inside the chip, and maybe also as shoot-through current. These are the real reason decoupling caps are needed: those transitions are quick, and if the supply can't keep up, your logic may end up not logic-ing correctly because a certain logic gate didn't get enough juice to update it's output in time for the next one to react in time...
@@laurjoost9317 Thanks for the explanation.
Since the donationware software from Saturn is used throughout a lot of this video, it would have been nice to have a link to them or mentioned that some sort of commercial license was paid since this is a commercial company using it. Beyond that point, this is a great video.
Thanks! Your video content is the safest and most useful
Glad you think so!
a real design flaw is to put a 48 volt backlight power trace next to the data trace on the ribbon cable to the display where it could arc over and blow the cpu.
on certain macbooks there was a flaw where the 48 volt backlight trace was next to the data trace that goes to the cpu so if the backlight circuit was to arc over it would fry the cpu.
having the decoupling caps close to the power rails makes better security sense if you intend to pot the chip you can include the decoupling caps in the blob of plastic so it would not be so easy for a hacker to glitch the device and dump the firmware.
the apple air tag was hacked because apple placed the decoupling caps far enough away from the chips that someone was able to solder onto the the caps and glitch the device and bypass the built in anti dumping of the firmware.
I imagine even if you do that, people can xray the package and then drill into it with a stop until the potted in capacitor pops, and do the glitching attack then. I don't think it's a product security strategy to rely on; you really need good brownout.
@@SianaGearz the drilling into the die and destroying something on the die is exactly how the security on a video game console (i think playstation) was done.
the maker integrated some chip into another chip to make it impossible to get homebrew or linux on the console.
Can you differentiate voltage input section and secondary higher voltage section / voltage converter section. Thanks
Very inspiring and thoughtful video, congrats. However, there's something I just don't get it: in 4:10 you've claimed that for high impedance signals one must reduce traces width. I believe you, but there is any chance that you point me out to the theory behind such statement? My first thoughts are on impedance matching fact, however I want to be sure, and if I'm wrong, to understand your claim Thank you in advanced! 😀
A thinner trace has a higher resistance, and resistance maps directly to impedance at all frequencies. It's not a "high impedance signal", it's a high impedance input. A signal doesn't have an impedance, impedance is an attribute of a circuit component.
For the sake of intuition it is quite useful to think of electrons as compressed air in a rigid system of pipes. Voltage is directly analogous to pressure in such a system, current is analogous to the mass flow rate of air, power is still power. Imagine you're designing an air compressor. If you use a big tank, you need a big motor and pump if you want to be able to fill it up to working pressure as quickly as a smaller tank with an equally smaller motor. To fill a larger tank to the same pressure as a smaller tank in the same amount of time, you need a higher mass flow rate out of your pump. The motor and pump are analogous to the source of your signal. If your signal source is very small, and only delivers a small amount of current, you want to use a smaller tank (i.e. a thinner trace) to store that current and build up a voltage you can measure.
Alternatively, think of every wire as being connected with a capacitor to ground. This is actually how we model wires in sensitive applications, using a "transmission line" model. A thinner trace has a smaller capacitance to ground simply because it has a smaller area. The impedance of a capacitor is inversely proportional to the frequency of the signal, so a thinner trace can carry higher-frequency signals with less power loss than a thicker one.
It's directly related to the previous section about track spacing. Greater spacing reduces coupling between traces. A narrow trace will allow greater spacing while using the same route.
Working on my first PCB. Love the content you produce.
I was about to say now try to route the traces after decoupling capacitors are placed, then i watched the rest of the video. But if you are using cases bigger than 0402, it is impossible to fit as close as in this video.
Is there a DRC rule to check if trace runs over GND?
You really good at explaining thank you
Glad it was helpful!
Very cool, thanks! And also thanks for the extra work I have to go back and undo all my mistakes :D
Keep them coming..this is very very helpful....a big thank you
Need more, Phil's I like your vids.
Do more videos please 😊😊
Hi, thanks for the nice video.
At 9:50 you place the vias to the power & ground plane between your de-coupling capacitor and the chip.
Wouldn't it be better to place the capacitor between the chip and the vias to filter out the most amount of transients before drawing from the plane capacitance?
Thanks
Phil, thanks for pointing out the need to avoid thin annular rings... I presume problems can arise due to drill tolerances?
Thanks! For small annular rings we need better tolerances/alignments for the drill hole. The drill hole will never be perfectly central to the via, so a smaller annular rings requires a more precise drill.
Also watch out for too large of an annular ring. Larger vias aren't always better, In the QFP design Phil was showing too large vias will most likely unnecessarily swiss-cheese the planes by the time routing is complete. General rule of thumb is to use a 5 mil annular ring unless ruggedized/class III then use 6 or 7.
Awesome video, thank you Phil
PHIL!!!! I'll always recognize his voice...
Hi Egor! :)
Awesome, especially last one advice!
Great advice!
Glad it was helpful!
Decoupling caps should be as close as possible to the IC but the vias to the power/ground planes should not be placed between the cap and IC. To minimize noise you want the majority of the required energy coming from the cap and not the power rails. So have a thick trace from the cap to the IC to allow for short bursts of energy. But then "charge" the caps using a smaller trace to a via adjacent to the cap but opposite from the IC. This results is lower surge currents to/from the power rails and helps reduce overall noise. In general, keep the trace between the cap and IC twice the width as the trace between the via and cap.
Why does Altium not use fluid curved tracks which are calculated on the "repellent" formulae that I learned in 1976?
I have a big doubt, that it's a good idea to place vias between decoupling capacitor and IC. I think it's better to swap the capacitor and vias placing.
Yep, useful or me as a beginner, thanks man.
Thanks, Kees!
yo bro, really thankya. Big respect
Glad it helped
Hello, great video.
I'm new to Altium and I have a question:
When designing my pcb, I imported my components and I try to connect my pins or rather the pads of a component between them.
When I try to connect 2 pads together, I manage to make my trace start from the center of my 1st pad, but I cannot connect this trace to a 2nd pad. The trace avoids the pad.
Do you know where the problem comes from and how to solve it?
Thank you in advance for your precious support 😊
Cordial greetings.
1: Do you know where the problem comes from?
2: Do you know how to solve it?
Thank you in advance for your precious support 😊.
Cordially.
Sounds like the second pin isn't on the same net as the first, try double checking your schematic to make sure the pins are all connected correctly
Decoupling capacitors should be placed between vias and pins. Because the current choose the shortest track and the lower impedance. If the via is placed between the decoupling capacitor and the pin, the contribution of decoupling capacitor will be significantly lower.
Altium. More of this guy. He did great.
It worked! Tank you sir.
Glad it helped
Thank you Phil!
using this and never lagging
Nice video, it works!
Good to hear!
ITS REALLY WORKED LOL THANK YOU DUDE
Great content.
3 times did not start, but then it worked
Great stuff!! 😀
Yo phil's here!
Highly recommend checking out his channel ( Phil's Lab ) for more advanced stuff. I learned alot from his videos.
Thank you very much!
Danke Phil!
Tysm, did everything as described
Glad it helped!
Golden advices!
Thanks!
Saturn setting had a 10mm power conductor length, unusually short for routing a power trace, should at least typed in 30mm.
Worked, thx
Heyyyyyyy It's Phil !
Great explanation.
Thanks!
Great stuff!
Thanks, Christopher!
Its working man!!
5:20 Length of the conductor is only 10mm(!) so of course those amps looked crazy high... Remember also to take consider the length of the conductor when calculating the proper width for your traces.
Good video. I just have a doubt about putting vias on decoupling capacitors between the IC pin and the capacitor pad. Usually I put the via before the capacitor pad.
It depends on whether you have closely spaced power and ground planes. In case you have a multilayer board with ground and power layers directly under the IC with few mils separation then it is as you stated, IC pad => via => cap pad. In cases such as 4-layer or 2-layer boards, it has to be via/trace => cap pad => IC pad.
The goal is to have a local energy reserve with minimal inductance for the power pads.
@@km-electronics1 One of the software engineers I work with found this video and linked it to me asking the exact same question. I kind of struggled to answer.
Is this video saying that placing the vias between the cap and the IC reduces inductance when compared to placing the cap between the via and IC? Or is it saying that it reduces the inductance to have via, cap and IC pins as close as possible? The interpretation of my software engineer friend was the former example. I’ve always put a preference on IC > cap > via, or having via in pad (other requirements allow me to do this), and only if needed I’ll do IC > via > cap, but only on low speed signals and large capacitor values.
How does IC > cap > via compare to via in pad (via in the capacitors pads)?
In Phil's example, placing the vias between the cap and device is usually fine because of the frequencies generally associated with a MCU. In this case the main goal is to decouple the device from the PDN while it is switching by supplying the demand for energy quickly enough to limit voltage transients from forming on the plane. Bypass cap placement (as used in analog circuitry) is more about filtering noise that already exists on the planes from getting into the device, potentially being amplified. In that case you absolutely want to have the cap between the device and the vias. PDN capacitor placement decisions often come down to digital vs. analog concerns and the ability to route a low impedance path at the frequency of interest. General rule of thumb is the smaller the capacitor value, the less layout induced parasitic inductance can be tolerated in it's (both forward and return) path. This is why the smallest value caps are always placed closest to the load and load return pins. The discussion of placement and routing should include the value of the cap, and this one is most likely in the .1uF range, not 1pF.
Hi as you said we have to good spacing between traces it's a question for me if i have good space between my traces but i fill this space with ground plane can make crosstalk or noise?????
Crosstalk will always occur between two traces, it’s just a matter of whether or not you notice the crosstalk or whether it’s actually measurable.
Take a look at this other video (th-cam.com/video/K1ob42Pv74Y/w-d-xo.html), it shows different situations where adding copper between two traces can increase noise in some cases, depending on whether the copper is floating or terminated to the trace’s impedance. That video looks at guard traces, but filling with copper between two traces is very similar to a guard trace, it is usually just much wider. The increase or decrease in crosstalk also depends on whether you are looking at striplines or microstrips.
@@Zachariah-Peterson thanks ... iknow what I have to do now i alway doubted it to put ground between some traces in sensitive areas or not.
Can we convert smd component to through hole in pcb layout
Nice Tips
Thanks, Simon!
So nice
thx and subscribed
Welcome!
Hello, where download saturn pcb design toolkit?
For some reason unable to download Saturbpcb tool kit. Anyone facing this?
good good😀😀
You need a really big board to use 0.9 Meter vias. 6:18
You forgot to mention, that people should stop using signal, gnd or power plane, gnd or power plane, signal stackup. It leads to all sorts of signal integrity and EMI problems. Signal and routed power, gnd plane, gnd plane, signal and routed power should used instead.
At th-cam.com/video/D0X76Kbf8fQ/w-d-xo.html are you really saying that a narrower trace is inherently less subject to crosstalk, or only that narrower is OK, so it is better to use that extra space to increase separation from the nearest neighbor?
How DO YOU OPEN A setup ALL OF THE TUTORIALS START WITH A setup
Kindly put an video for fabrication process like in topic Gerber generation fab details and drill generation
Hi Phil
Amazing content as usual! Thank you for this.
I have the same comment as last video at 9:54 regarding the positioning of your de-coupling vias in relation to the IC pads and the de-coupling cap. I realize you probably had this video made and edited and ready to go but I wanted to re-iterate that the ordering is incorrect.
Hi again, Sorry for not having gotten back to your comment on the last video. I attended a Rick Hartley seminar and he stated that this is the preferred placement for vias to minimise both inductance to (widely spaced) planes and decoupling cap (happy to share the relevant slide with you). Now, for routed power this is slightly different and it is preferentially to do GND via -> cap pad -> IC, as you state. In an ideal world, one would have GND(/PWR) vias directly next to the both sides of the MCU pads and the cap.
@@PhilsLab Can you share that slide? I was discussing with my team - and everyone agreed they had been taught vias outside the decoupling cap. Interested to see the details on this recommendation.
@@jerrybeckmann1323 Jerry, I don't have that referenced slide, but check out Howard Johnson's article "Bypass Capacitor Sequencing." He favors the approach with vias between the IC and the decoupling capacitor to create a lower impedance path.
Interesting. I had learned that the via was a larger inductance than the trace, so the capacitor was creating a mini power plane to handle the local ups and downs from the larger power plane. Much more of keeping the noise of the power supply reaching the pin.
I’ll have to do some simulations to see the impact here.
Good read :)
Apperently TH-cam wants me to watch this video.
Can I ask wjat a PCB is?
Shouldn't the vias be on the other side of the capacitor?
It should. I was right. The point of decoupling is to remove noise. Such purpose is defeated if the via supplies power to the ic directly.
Nope, this is fine. This is not analog nor PAM4, just an MCU. Some of the highest speed devices come in BGA packages where the vias are almost always between the cap and the device. Granted the high-frequency caps are moving to being on chip now, but the .1uF mid-range decoupling is perfectly fine connected as Phil shows, and if 10uF or above does not need to be near the device vias at all.
@@ekenedilichukwuekeh4647 The point of decoupling is to limit transients from forming on the plane, the point of bypassing is to remove noise. Priority of one vs the other, and the value of the cap, helps us make the decision on how to connect.
You have no idea how many mistakes somebody van make. 🛠
i'm pretty sure that the last one, at least as demonstrated, should not be even considered to be a mistake, not one little bit. Just the solder joint on the chip the trace goes from is probably an order of magnitude more of a disruption, than the tiny bit of opening of the round plane below a tiny fraction of the length of the track.
cool, can you make a tutorial on how to do that on KiCad?
says premiers sept 8th @ 8:30am
it's wrong your distance between chip and your via and cap 3.3v is very closet and while a person that want solder a chip have a problem or in repairing or testing
👍
Rooting? I think you mean routing.
Music is not necessary.