I'm a hobbyist (2 layers PCB, audio) and I have been always taught that coupling caps should be on the same layer as the component being decoupled. I belive it makes sense, since vias have parasitic inductance and resistance (also explains why having multiple vias help). Thank you for the videos, they help me a lot!
This matches what most chip manufacturers say about decoupling caps "They must be as close to the power pins of the chip as possible" taken quite litterally this means on the same layer and right next to the pins. This matches your results perfectly.
What I really like about you and your videos, is that you actually dive a lot deeper into the subject. Most people (even many professionals) just repeat something they have read or heard somewhere without even investigating. (And also say it on such a way like it's factual) I would really like to see so practical measurements to see how accurate these simulations are. Since vias always add some resistance and inductance, it makes sense that a direct connection will be better I think. I am curious about some hybrid approaches.
Thank you P_Mouse. PS: That is exactly what I have in mind when I am creating my videos - I keep hearing a lot of "facts" and many are exactly opposite, or people just repeat what they heard somewhere and then ... it's super difficult to say what is actually true and how important it really is for real designs. And that is what I am trying to find out in. Just need more ideas for next topics :D
@@RobertFeranec I have whole lists of these kind of ideas or questions. Although not only related to PCB design. But mostly also more from practical design. One example is still the excessive amount of via stitching vs proper pcb design.
@@p_mouse8676 If you would like to share some interesting topics, I can have a look. No promises, but if it is also interesting for me and I find someone who can help, I always try to do it. Just send me an email to info@fedevel.com. Thank you.
When people say the location of the capacitor doesn't matter; they are talking about the bulk capacitor(C>100uF) which is more effective at lower frequencies. For decoupling capacitors location matters hugely. Moreover, if you build and measure the real results, I propose a better method for the circuit #43. You used multiple power planes. But if you use power and ground planes interchanging from top to bottom or vice versa ( P-G-P-G) you can create a good interplanar capacitances parallel to each other. This method is said to be much better since the interplanar capacitance has very small ESL compared to chip capacitors.
this is true, but this is only partial inductance. You still have to get from the cap vias to these planes and from these planes to the ASIC or other DUT
Oh, I believe that people / articles were talking about decoupling capacitors. That is why I was so surprised. Need to find them ... PS: Good idea with the power planes. Thank you.
To me the simulation results without vias look totally fine. To my knowledge, vias have non-negligible inductance which increases the impedance at high frequencies a lot. So a direct connection is always better than vias.
You demonstrate the effect of the position of the cap by showing one very far compared to one in the center. I would be curious of the result of a cap very near the power pins! Thx for the video, always fun to play the PCB version of Dora the explorer ;)
@@RobertFeranec Yes, exactly my thought. I wonder how a single capacitor directly at the sink without vias would perform. Which is, to my knowledge, the recommended way of connecting decoupling capacities
Great Video! If possible, I always try to place the decoupling capacitors on the same side of the IC and draw a direct connection (and not separate vias for capacitor and power pin). In my understanding, I have two reasons: The direct connection creates a low inductive path. That also applies for your example with a the thin, but straight direct connection. With separate vias, the current from and to the capacitor has a more odd path to follow, which results in losses for higher frequencies and impairs the decoupling effect. The second reason is: You want to have the decoupling capacitor as the reference, not the decoupled plane around the IC. There might be still some current peaks crossing that take effect. This applies for forward and return current, so to say Power and Ground. That is why I also try to put the vias behind the decoupling capacitor, not between capacitor and IC.
this may not be a good idea. Watch for another via. The question is always the sum of the partial inductance terms. If there is a large separation between planes (say 2 layer or 4 layer PCB with symmetrical thicknesses) then the inductance of a surface trace is very high. If the two capacitor vias can be very close together, field cancellation will greatly reduce the inductance. This is in many of my lectures and bootcamps.
Very interesting! Especially the performance of the thin top layer traces with no vias vs. planes with vias. After some thought I would suggest that the remarkably low impedance is partially due to what the simulation is measuring. Specifically, it appears that the simulation is calculating the impedance from the S21 insertion loss parameter which measures the voltage on the output pair given a varying voltage/current on the input port. For a high speed decoupling capacitor I would think that the S22 (or S11) return loss parameter would be of greater interest which would measure how much the voltage on the output pair changes given a varying output load current. I think that the calculated impedance based on S22 would be much higher for the long skinny top layer trace case. Thank you very much for the wonderfully informative video and keep up the great work! I would love to see some PCBs actually built and tested with a network analyzer for both S21 and S11 insertion and return loss measurements.
Robert, very nice and useful video and very surprising results! If I understand right, the loop inductance plays the main role in degrading the PDN quality. As well VIAs also degrade the loop inductance according to these results (due to their inductance). Placing decoupling capacitor far from the desired point on the board (like VCC & GND of some component) significantly reduces the influence of this capacitor on this desired area. This is the reason why it is mandatory to place as many capacitors (near all power supply pins) as possible. When we place the capacitor between two parallel traces, the travelling wave (noise) is shorted by it, and do not propagate towards the load. When this capacitor is placed far away aside, it shorts the wave propagated towards it, but not the wave propagated towards the load, and can even create travelling wave. This is how I imagine this phenomena. So, according to this video, the best way to place the decoupling capacitor is on two traces between VCC and GND vias and an appropriate componnent's pins. Please correct me if I'm wrong.
The parasitic capacitance on the example in the upper right is less since the the air is a much lower dielectric constant. Much less inductance to overcome. Results in a much lower ESR. We always use thin trace for sense lines for this reason. Good topic Robert, very well presented.
Very curious to see the real board with the real time measurements. Your videos are gem, you are really making hardware things very easy to understand. Thanks for all the effort you are putting.
Hi Robert, I really appreciate your investigation on that topic. It made me think a lot and the following question arised: How would simulation change, if you would only connect the capacitor's power and/or ground pad directly to the IC's pads and not to the source pads. I think this case would represent a very typical design approach. In practice, many of the "good "solutions presented in your video can't be implemented, since board area is limited. If you like to spend more time on that topic, it would be interesting to take a look on more simple/practical designs. What I mean by "simple/practical" design is: - Place one or two capacitors of different sizes (e.g. 1u + 0.1u) really close to the IC's power pad (capacitor and IC on same board side) - Connect the power pad of the capacitor directly to the IC's power pad with a wide trace - Connect the power and ground pad of the capacitor to power and ground plane by via, respectively Then you could go ahead and simulate following effects on PDN impedance: - Number of vias connecting capacitor(s) to planes - Position of vias relative to power/gnd pad (above, side, both) - Via diameter / via pad size - Capacitor orientation relative to IC edge - Capacitor's power pad connected directly to IC vs.capacitor's power and ground pad connected directly to IC I think this investigation is very helpful for many board designs and maybe it would be worth a short video.
From my understanding, the placement is important from loop-area standpoint but the vias also add a big problem (they're inductive mostly with capacitance to the inner plane holes). It's best to use the same layer from the capacitor to the IC power pins using very short traces (if possible) and then have the via to the power planes. This way you avoid extra inductance and you have the local decoupling with the lowest impedance to the IC (this is why you want capacitors in the first place - for high frequency transient energy). For a more realistic simulation you should have an IBIS model of an IC with dynamic switching because the transient behaviour of an IC during switching is a non-linear current draw. The different frequencies will see different impedances due to the different current harmonics.
I had experienced your finding about cap on the same layer the hard way - EMC testing. It is all about loop area and inductance. After putting power inductors and power caps on the same side of the board, design passed EMC. With caps on the bottom we as engineers get sloppy, we forget that energy is stored in the dialectic between planes and cap plates. So if we changing plane (which we do, image current flow direction), we increase impedance a lot. I use that for filtering when I need to. If we keep decoupling cap on the same layer, we get current flow from the cap (directly between +V and GND pins of IC) on top layer, then this current is supplemented by current flow from inductive power pins. If we do not use direct connection to cap, then current flow from power plane to IC pin (through inductive vias), so voltage drop and ground bounce occur and only then additional charge comes from the cap (through inductive vias).
Very illuminating video! 25:20 I keep going back to the hydraulic analogy, because it works.Which will give you more immediate access to your local water reservoir: a long narrow tube or a short wide pipe? Of course you're going to have less impedance if the power traces are on the same layer as the capacitor; there's always going to be some additional impedance through a via, like resistance through a straw. In fact, if you plan your stackup right, you can even exploit the impedance of a via from a power plane as part of an RC decoupling filter. It's not rocket surgery, it's PCB materials engineering.
Absolutely fascinating, thank you for this! I’m definitely going to look for your other videos on this subject. And I second the request for physical measurements to back up the simulation. My guess is the results would not be identical, but the ranking of results (which designs perform better than others) would remain the same. I would be _very_ interested to see the load changed to a SMT connector, to simulate (or physically test) the real world case of the load being a SMT device, like a QFP or QFN device. There is debate over the best placement of decoupling capacitors in these situations, and to me your result at 23:40 makes absolute sense; there are _no_ vias between load and decoupling capacitor, and to me that would produce the lowest impedance between the two. For this reason I _always_ place SMT decoupling capacitors as close as possible to, and on the same layer as, the load device. What I take away from this is that the two biggest factors are (1) capacitor placement as close as possible to the load, and (2) avoiding vias between capacitor and load. Then, if you _must_ via between the two, (3) maximise the number of vias in parallel, (4) maximise the number of capacitors in parallel, and (5) maximise the number of ground and power planes in parallel. Lastly, it is worth maximising trace width and minimising trace length, but after the above steps these make only marginal improvement.
Robert, Superb post thanks so much for this. You push everybody up to a better level. I suspect the good result is the input and output inductance to the cap.
This is very good, thank you! It would be interesting to see the result when there are vias by the capacitors, and then they are connected with traces to the power pins but not the supply. That seems likely to happen in a board layout.
Excellent work, Robert! Years ago, some technical articles I read, either from Microchip or Cypress Semiconductor heavily stressed the effectiveness of placing decoupling caps near the power pins and on the same layer as the power pins of microcontrollers. EG in the case of a quad flat package. You can feed the pins their power through vias, but you want the decoupling caps between the vias and the pins. As you say, you can't always have things arranged this nice, but it's something to target when you can. I like your confirmation of surrounding power feed pins with vias improving performance. I had often suspected this would be the case. Thanks again.
Thank you, Robert! Great video. An answer to one of these every day questions developers come across. It really helps a lot to get a better feeling what is good or bad when placing decoupling capacitors.
It was good to demystify the "vias on the side are better than vias on top of the pad". Very little difference indeed. In my opinion, the interesting layout would be having the capacitor on the same side as its load connection, but the input supply coming through vias from the power planes. This is a very common implementation in DC/DC power supplies. Check the typical symmetrical CIN decoupling implementation suggested in most power devices from MPS or TI, it has minimal impedance and the EMI emitted gets canceled out by the opposite direction of the fields.
Same layer connection should win every time. Extremely small inductance in series with the capacitor compared with vias in series with the capacitor. Luckily the simulations confirmed what I guessed in that regard. Very nice job making this video 😊👍
Hi Robert, this is amazing stuff! Thank you so much! After reading so many application notes, books and following seminars on the topic, it's your videos that make it all come together in a way that is easy to follow, and you can actually *see* what happens. Even when I do indeed understand that it's a specific simulation and results may be different on a real board. Thank you for making the theory practical so that it's easier to apply in real world board design. It would seem that the impedance - mostly inductance it seems - between the power connections and the capacitor has the most influence of how much total impedance there is at 100MHz. I see the impedance curves increasing with frequency which also seems to indicate we're looking at inductances having the most influence at those frequencies. All this time I have been thinking about how to connect *capacitors*, and now it begins to show that you may instead have to think about how to minimise *inductances* in the connections. I was as surprised as you were at how good the one with the long thin traces and no vias was. It made me wonder about how much inductance a via really has compared to a long thin trace like that. There must be a crossover point somewhere where it's better to use vias or multiple vias than a trace. In any case, I am making a mental note to make sure my power connections are done with *wide* traces wherever I do need to use traces. What I really wondered about is this. You placed the single capacitor right in the middle between the source and load pins. What if you placed it right next to the load pins, similar as you would do with an IC's power pins? Would you be willing to consider trying that? A second question is how stackup comes into play here. I would assume there is a difference depending on how close the power and ground planes are in the stackup?
Thank you Christe4N. PS: Exactly the same for me - I also changed the way how I look at connecting decoupling capacitors. We may be doing follow up video with some other examples.
When it comes to decoupling, vias are inductors, so if you can, eliminate them - this is why having the cap and power plane on the same layer is so helpful. When you can't eliminate them, placing a few vias in parallel helps - up to a point - the nth via only provides 1/n improvement. Parallel power and ground planes do add a little extra capacitance, and you can calculate how much using the area, dielectric thickness, dielectric constant, and the capacitor equation. What you will quickly figure out is that the little ceramic caps provide MUCH more capacitance than the power and ground planes, and they have a better Q. A common problem is that the parallel power and ground planes are a much better transmission line than they are a capacitor. This means that when a slug of current gets pulled out of the planes at one spot, that voltage dip travels across the whole rest of the power/ground plane at roughly 185ps/in. So you want to make sure the chips take that current out of the decoupling cap, and NOT the power/ground plane. So make sure the power via is NOT between the chip and the cap! Otherwise, much of that current will come out of the power plane rather than the cap. A properly sized ferrite bead between the cap and the power plane can help insure that current comes out of the cap first, and what gets pulled from the plane comes out slower. Another thing to keep in mind with the fast edge rates on modern chips, you have to consider that you don't see the whole capacitance of the entire power / ground plane pair, but only what is within the "lumped element" radius of power pin, due to the speed of currents in the PCB. This works out to roughly 0.9 inch for every nanosecond of edge time. That is, a 1ns rise time will only see a circle of about 0.9in radius of the power / ground plane pair of effective capacitance - after that it's a transmisson line. For large chips like FPGAs, you'll want to keep in mind i = C * dv/dt. Each I/0 pin will have to drive some capacitance C at the device's rise or fall time, dv/dt. This will allow you to calculate how much current each I/O pin will source or sink when it switches state. It has to pull this current out of its associated power pin. If you have a 32-bit wide bus switching pins at the same time, then you have up to 32 times that current switching all at once. You'll be surprised at how large that current can be. Fortunately, the same equation can reconfigured to determine the size of the capacitor you need to limit dv/dt to a safe level.
Great Video - an EMC seminar once told me to run power trace across the capacitor, directly to your pin of the IC you are decoupling (Same side). So this adds up with what you have said here. Would be great to see this boards in action.
That is why I commented in previous video that it is better to have copper under component and not be worried about making a short circuit to the component :-) Wide tracks on the chip side are very important! For smaller DC/DC converters I have around 2mm wide tracks. At 0603 capacitors one via is under the component and another is behind it. After 0603 come 1206/1210 capacitors which have multiple vias under it for both connections. Vias have 0,3mm hole with 0,5mm copper ring. If space is not a problem I have even wider track for Vcc on L1, because it forms very good capacitor with GND on the L2. Much better than capacitor between L2 and L3 in 4L board, because of less vias and smaller distance between planes.
Very cool video. Your last simulations are correct for the behavior of the capacitor impedance. But the split plain on the top side of the board is still a dipole. If you make it in physical boards, probe it with a near field probe to see the difference between full ground plain and split ground and power plains. I’m guessing you will measure impedance through the cap is amazing- but you still radiate with the modes of the plains. I definitely learn something from these videos. Keep up the amazing work! Thank you.
Yes please! Much interesting and I am much curious about the actual impact of the parasitic cap-to-target (basicly direct connection vs via connection) in the real world. As always, you have a very good approach to those kind of complex and long debated topics. Keep it up!
Hi Robert! Your video is highly informative, get to see which layout has the lowest impedance. A bit of warning for vias planting near the pads, as this would leak the solder into them, thus weakening the solder joint on the cap leads. With a weak solder joint, weak connection, bad impedance. Thank you and keep sharing!
I only recently came across this channel, but the quality is superb! Seeing results on actual boards would be fantastic, but I suggest building a few instances of one of the single cap circuits to get a sense of variation across process.
very useful video, always wondered how the via placement on decoupling capacitors could affect its effectiveness. not very surprised for the better result on the direct connection (no vias) as I see vias as 90degree turns on a track. i hope you build these boards for real and test them, i think more surprises would come. thanks for sharing!
Thanks again @Robert, It would be interesting to see the result for 1 capacitor close to the sink pin. As we usually do in our design. Comparison between narrow and wide traces... Good idea for real board testing and comparison to simulation. You rock!
Thanks for the comprehensive overview. Yes, please fabricate. I'm always skeptical of simulations - we'll see if it's warranted. Very valuable information as always!
Your investigation is terrific. I would like to see the real assembly measured. But one I would like added is say some spread of bypasses between the in/outputs, but also one at each of the input and output nodes on the same side, thus see if improvements will result from bypassing at the in and load nodes not just spread across the board. Significant is the improvements by NOT having connection by via. This is quite critical as I tend to make bypass on the direct connection to device power lines not bypass to a via to power plane near where also the device reaches power plane by a via. Hope I have made that clear what I mean
You should also make a poster showing all the different options from worst to best! Would be a great reference during layout to know how you might move the capacitors to optimise the PDN.
I cannot recall where I heard this from. Someone told me that the efficiency of decoupling is all about the loop inductance (from the cap itself to the power pin). A via is an inductor as well as small traces and long distance. So a good decoupling is to minimize all 3, if you have space!
Thank you. Great video. Yes, please build the PCB. I would love to see the actual vs. simulated results comparison. Great work, Robert. I first found you back in 2012, when I was working with Altium.
That was interesting! If I understood correctly, you set the input on the left and the output on the right, so this uses capacitors as filters, not decoupling... If you set the input and output port on the same side of the pcb, it is more like the way a chip sees the impedance of the PDN at its power pin, I think you'd get different results. This would be interesting to simulate.
Hi Robert, great video. Keep up the good work. I would also appreciate to see you actually build up this board and verify your simulations. That might shake up some "common PCB rules". BTW: I always recommend your AD videos to people who are new the software. Way more efficient, than learning it by the AD manual. So, thanks for that too.
Hi Robert, great video! Really interesting. It will be amazing if you measure this! It make sense that not using vias yield to lower impedance, because they introduce a inductance that will increase the impedance with a increase in frequency. That is why is better to use multiple vias in parallel, because you reduce the inductance (series) between the capacitor and the plane. Greetings from Argentina!
Thank you for creating this video! This is a super useful reference for everyone that's designing PCB, especially since trace width component size and placement is difficult to understand what effects it might have on a circuit. It would be even more interesting if you built this board and did some actual measurements on it! I will definitely watch this video again the next time I'm creating a PCB, just to freshen up the memory!
@Robert Feranec, I’m not sure what the width of your board is, but the decoupling impedance is directly impacted by the length of the trace (including bias). So in the example of the one cap with direct connect on the top layer from PWR Supply to PWR Pin, if that total distance is less than the distance through the vias (not sure of your board thickness either, I didn’t bother converting from mm to mil), it would make perfect sense as to why you have a lower impedance. I would have loved to see an explanation and show the correlation between your decoupling caps and the decoupling formulas. Making the math come alive would be really beneficial for us all
Great video! Your channel is a treasure chest for every EE! Almost guess them all right and funny you posted that video I was wondering about that topic!
great video and very relevant to junior designers. please fabricate the boards and measure them - i'd love to learn about the instrumentation station + best practices to measure PDN
Around 15:00 you mentioned that you had heard that decoupling cap position may not matter if you have power plane and that your sim shows that it may not be true. I would say that your power planes are really far apart and therefore ineffective. Looks like your planes are +40mils apart. If you can, run the sim again, but this time, for the stackup, keep the power planes < 8 mils. Does placement of capacitors matter then ? From literature, its that the power plane provide most of the decoupling (when < 8mils) and physical decouple caps can be much looser.
I love your scientific approach to electronics. Awesome content! Definitely, I think it's worth doing checks of the real boards. Simulations, are just simulations :) Waiting for the next video!
Thanks Robert, fantastic work. In terms of additional simulations to try, I would be interested to know whether it was adding more capacitors that gave you better results, or whether it was simply that by adding additional capacitors that caused some to located closer to the load terminals (on the right hand side of the board), rather than being located in the middle of the board. Regarding using big areas of copper on the top-surface, whilst soldering the caps to big areas of copper (as in #25) gives a nice low-impedance, I suspect that the lack of thermal reliefs will cause production reliability problems during IR-reflow soldering. They would also be a nightmare for re-work, as you would have to heat up the whole copper-plane just to de-solder the capacitor. So, this might cause more trouble than it is worth.
Thank you Nicholas PS: Today, I was thinking exactly the same - if just placing some of the capacitors closer made the difference. Maybe another example to try ....
Hi Robert. It would be interesting to compare with the installation of one low-ESL capacitor. It should be significantly better than a single conventional one at high frequencies. By shortening the track lengths and increasing the number of holes, we reduce the external inductance and hit the internal inductance limit. We can further reduce the inductance only by paralleling conventional capacitors. According to the characteristics of the capacitors, we should get the same characteristics for one low-ESL capacitor and four normal capacitors. All connected with minimum external inductance. Congratulations again on the youtube button:)
It would also be more interesting to compare standard situations with a single capacitor and using two polygons (power and ground as in the first examples) versus a ground polygon and powering the track (in the same layer as the power polygon), via a capacitor.
Awesome one....I usually have fights and arguments with my peers on the same topic. I loved the way how simply you have explained how to analyze PDN impedance curves at 5:42....Thanks robert...looking for more high speed pcb design videos...!!
@@RobertFeranec Hi robert, here's an video idea. Recently I started doing some RF boards for wearable devices. The entire design was alright but things started taking bad turns when coming to the RF section. The very big problem I had is to do impedance matching. I also heard this is a very big problem with lot of my hobbyist friends and makers out there as this process would need equipment like VNA's. So can you please shed some light on this topic by making a video on how to use VNA to match the impedances?( by taking a simple 50ohms boards would be enough.) Hope you would consider the request. Would love to see a video about this on your channel.
YES you should build a few boards and measure them. You should also add a board with single cap right next to the load pins (basically equivalen to populating the rightmost cap only on your 8 cap designs).
Hi Robert! Very interesting video as always! If I had to justify why direct connection is better, I would say that it probably has better results because it is the shortest connection (so less inductance) and also there is no via (so shorter connection and no via parasitic inductance). Preferably use the variation with the thicker tracks or polygons. As for the Capacitor size, I think it would make a bigger difference if we had to compare smd with through hole packages as mr.Bogatin mentioned in one of your previous videos, but maybe 0402 with 0603 for example would have little difference here at least for relatively low frequencies. Maybe it would be more noticeable for higher frequencies? Manufacturing and measuring the real pcbs would be interesting I think.
You seem to be in an especially good mood in this video, very pleasing to watch, thank you. I would certainly be very interested in seeing your simulation results verified by measurement, also would you consider having a look at specialty multi terminal packages like smt feedthru, x2y and lga/bga, this would be useful as most of the material available is from entities trying to sell these things
Thank you for another great explanation. These videos are invaluable. I don't know if I will ever have the chance to design something > 5MHz, but even in that domain, the conclusions are useful.
Thickness of the core in this 4-layer stack-up is HUGE (about 1mm, like in most 4-layer stack-ups). I think that's the reason that capacitor placement appears to be more important than connection style. I would definitely reduce the distance between power and ground plane to something like 0,1mm. That is more of a "real world" value for boards where one really cares about PDN impedance.
Another great video in the decoupling series. As I understand it, local decoupling (10n - 100n) needs to be at the pins, but bulk decoupling (1uF and above) just needs to be connected on the planes. It would be good to add these to your test PCB, also. It is not clear from your excellent plots how the frequency of the ESR notch is affected by the different connection types. Does this matter? Another test would be what effect does putting the decoupling capacitor AFTER the output pins have, compared to having it BEFORE the output pins? Your test PCB from part 1 has the local decoupling after the CPU power pins, but the common advice is to make the PDN track go to the capacitor and then to the device power pins. Does this really matter? Keep up the great work. Look forward to further involvement from Steve, Eric, and Rick! Please build and test the PCB. Theory is important, but real measurements confirm the simulator's predictions. P.S. I think there is more to learn about the ferrite beads from part 3.
I think thin traces with no vias achieved such a good result because You minimized prasitic inductance from vias. but when You do place one via, its better to have multiple in "parallel" because connecting inductors in parallel effectively decreases their inductance, and vias are basically small inductors.
Is there a difference if you place 1 capacitor close to output pins, or 1 capacitor close to power pins, or 8 capacitors between? I miss this comparison in your simulations. btw. nice video ;)
Hi Juraj, From a class attended with Prof. Todd Hubing, he mentioned this aspect. You have to consider where is the power and gnd plane to decide where to place the cap. You have to think about the current flow path and consider which plane needs decoupling more (quite often the farthest plane in the stackup is where you place the decoupling cap). A usual stackup is sig, gnd,pwr,sig (im not recommending this stackup, just for eg). In this case, I would place the decoupling cap close to the power pin.
Great video! It would be interesting to know how thermal relief affects PDN. How big is the difference between a direct connection and through thermal relief.
Hi Robert, I think your results do make sense because of your stack up - GND and PWR are >1mm apart. Signal through the same layer traces will have less inductance/impedance than through the vias. I would be interested to see the same simulation on closely spaced power planes (
Big thumbs up for this video, but the parallel power and ground planes on every layer are contrary to what one of your previous experts, Eric Bogatin, advocates, which is alternating power and ground planes on the PCB to minimize EMI. Would like to hear his take on this...
Re: 23:38 - the two parallel lines create another capacitor - two conductors with a dielectric between them, so it makes sense that the results are better.
Very cool. I wonder if this means that QFP / QFN parts would have an advantage over BGA devices, since it could be practical to connect the decoupling capacitors to the pins directly without vias. Although, it's likely that the reduction in inductance from the BGAs would have a larger impact. If you have time, could you try the following configurations: 1) A T connection. Where the capacitor is directly connected to the power pin, but only connected to the power plane through vias mid-way through the connecting track (like a T where the base of the T is the via to power / gnd). 2) An L connection. Similar to the T case, you could look at the case where the via comes after the capacitor in the path (sort of like your direct connection cases, but the trace to the power input is cut and replaced with a via to the power plane instead). I was going to suggest also placing a capacitor directly on the power output pins on the bottom layer, however, due to symmetry, you have effectively already tried that. It would be very interesting to see if real life holds up to the simulations.
@@RobertFeranec To test the QFN/QFP vs BGA, you could probably simulate the leads via adding inductors between the connection trace and the simulation measurement points. Though you would have to find realistic values for the inductors... I did a quick search and found an app note by TI (AN-1205), which models different package leads as a RLC network - perhaps that could be helpful.
It would be nice to see the case when you connect the VCC net of the capacitor directly to the pin, but the GND is connected through vias. I think this is a pretty common scenario when designing PCBs. Would be nice to see there does it stand in the chart.
Nice video. However, since you are using a 4 layer board the spacing between power and ground planes is relatively large which makes the inductance big. That is why your results are sensitive to capacitor placement. If you used a small spacing between power and ground plane like 3 mils then the spreading inductance would be much lower and not as sensitive to capacitor placement. Would be interesting to repeat this using 3 mil spacing.
I love that your are actually simulating many different cases to try to figure out how this works, rather than just reiterating some rules of thumb that are out there. I think your simulations are correct in some regards, but some of the conclusions might not cover the full story, so there are some further points that are worth making. First: You get impressive and surprising results with those long skinny traces to a capacitor between the source and load. This might at first seem surprising and I think the simulation is correct, but possibly not very relevant. I think you are simulating the shunting impedance between power and GND as it would be seen by a VNA doing an S21 measurement. So if you force the signal from port 1 to travel along arbitrarily long and skinny traces, then encounter a capacitor that shunts the power and ground trace with no parasitic inductance in the shunting other than that of the capacitor itself, the signal on the traces at the capacitor will be very effectively shorted by the capacitor (and almost all of the wave reflected back to port 1). The signal that continues towards port 2 (the load) will be very small indeed, again regardless of the length and skinny-ness of the rest of the traces. A similar effect happens with the examples of caps connected to the planes, but either right between the source and load or far off to the side. Most of the signal from the source will go along the shortest line between the ports, and if there is a cap there, it will effectively shunt the signal. If you had had much smaller separation between the power and GND planes, you would probably see much less of this effect as the signal would spread out more due to the decreased inductance in the plane-pair This kind of decoupling effect is relevant if you have a noisy power supply and a quiet load you want to protect form the noise. So for this case, your result that this layout is a good one is correct. However, if the load is also noisy (draws significant current at high frequencies), this layout is no longer a good one. The impedance looking into the load terminal (as you would see if you simulated or measured the shunting impedance as seen by an S22 VNA measurement at the load) is very high due to the large inductance in the skinny traces between the port and the cap. Most of the time (but not always) the most important purpose of a PDN is to provide clean power to loads that have noisy current consumption and thus are prone to disturb themselves. This does not seem to be the case you are simulating. To simulate this, you need to inject the signal and measure it at the same port. Or, if you want to do an S21 type of simulation, you could perhaps place port 1 on the top of the board and port 2 on the same through-hole pads, but on the bottom of the board. If you want to measure low impedances like this in the real world using a VNA, an S21 measurement from top of the board to the bottom of the board is a good setup. S11 or S22 measurements do not work very well to measure very low (or very high) impedances as they essentially need to subtract two almost identically large signals from each other and look at the difference, which is therefore extremely sensitive to small errors in the measurements of the outgoing and reflected signals. Second: A 4-layer board typically has a very large separation between layers 2 and 3. This is certainly true for the JLC standard stackup. This is not ideal if you want to have a low-impedance PDN on your board. So if you are stuck with a 4-layer board of this stackup and need to use layers 2 and 3 for power and GND, your conclusions about e.g. capacitors connected directly to the load is highly relevant, since there is so much inductance (and so little capacitance) in the planes, which makes it impossible to create a decoupled plane with a really low impedance. For more advanced boards with more layers (not usually used by hobbyists, but very common in the industry), one typically strives to have a much smaller separation between the power and GND planes. 0.1 mm is rather easy and smaller separations like 0.75 mm or even 0.05 mm is not too advanced for many board shops. This totally changes the situation regarding how important it is to have decoupling caps connected directly to the pins of the load (or right between the source and the load if that is the case you are interested in). Howard Johnson has in his black magic book a very neat and simple formula to calculate the inductance of a pair of vias connected to a pair of planes (converted to metric units): L=mu / (2*pi) *2h * ln(2s/d) Where: mu/2pi = 2*10^-7 H/m h = thickness of the dielectric s = center separation of the vias d = via diameter So, the inductance is much more sensitive to the thickness of the dielectric than the via separation and via diameter, although there is some reward to be had in optimizing all of these parameters. This formula can help estimating how important or unimportant it is to keep the vias a decoupling cap close together. The total inductance of the cap can be approximated as the one given by this formula, plus the inductance of the vias above the planes pairs, plus the inductance of the tracks between the cap and the vias, plus the inductance of the capacitor itself. Johnson argues that this formula can also be used to estimate the inductance of a distant decoupling capacitor as seen from a load by plugging in the distance between the load and the capacitor as d in the formula. So inductance increases only logarithmically (very slowly) with increasing distance. By the way: In multi-layer boards, there is a new factor to think of: Decoupling capacitors are more effective if they are placed on the side of the board closest to the plane-pair they are connected to, since this reduces the inductance of the vias that connect the capacitor to the planes.
Hi Robert, Something I observed also from your call with Dr. Eric Bogatin about PDN impedance is to look at impedance seen from the power port (pwr + closest GND pin) out towards the PDN network. In this simulation, is one port the input power and you are looking back from the other power port? I assume so. I have a question about placing caps close to the power pins on QFN packages. If we keep them close, sometimes there is not enough space to put a via and then I have resorted to putting the via on the other side of the chip pin. This would be a good simulation to run as the PDN network will be seen with via and the capacitor in parallel with it.
I't would have been interesting to see what kind of difference does it make if you are using thermal reliefs. I rarely use direct connection for connecting passives to power planes, that's why I'm wondering.
I think that for your multiple capacitor tests they might be best basically because there's at least one capacitor very near the output. I miss a test where ONE single capacitor is placed next to the output. My assumption is that this would be very good regardless of the type of connection. Also I tend to think that the smaller footprint capacitors should perform better at higher frequencies, but of course this should be tested before making a formal statement
Hi Robert, It would be interesting to see you testing these PCBs after fabrication
Thank you Vishnu
@@RobertFeranec Yes, please. We have almost no good pcb testing videos.
Seconded, this would be a really interesting exploration.
I'm a hobbyist (2 layers PCB, audio) and I have been always taught that coupling caps should be on the same layer as the component being decoupled. I belive it makes sense, since vias have parasitic inductance and resistance (also explains why having multiple vias help). Thank you for the videos, they help me a lot!
I put them, on the same layer when possible, I also put a via on the GND pad of the cap.
This matches what most chip manufacturers say about decoupling caps "They must be as close to the power pins of the chip as possible" taken quite litterally this means on the same layer and right next to the pins. This matches your results perfectly.
What I really like about you and your videos, is that you actually dive a lot deeper into the subject. Most people (even many professionals) just repeat something they have read or heard somewhere without even investigating. (And also say it on such a way like it's factual)
I would really like to see so practical measurements to see how accurate these simulations are.
Since vias always add some resistance and inductance, it makes sense that a direct connection will be better I think. I am curious about some hybrid approaches.
Thank you P_Mouse. PS: That is exactly what I have in mind when I am creating my videos - I keep hearing a lot of "facts" and many are exactly opposite, or people just repeat what they heard somewhere and then ... it's super difficult to say what is actually true and how important it really is for real designs. And that is what I am trying to find out in. Just need more ideas for next topics :D
@@RobertFeranec I have whole lists of these kind of ideas or questions. Although not only related to PCB design.
But mostly also more from practical design.
One example is still the excessive amount of via stitching vs proper pcb design.
@@p_mouse8676 If you would like to share some interesting topics, I can have a look. No promises, but if it is also interesting for me and I find someone who can help, I always try to do it. Just send me an email to info@fedevel.com. Thank you.
When people say the location of the capacitor doesn't matter; they are talking about the bulk capacitor(C>100uF) which is more effective at lower frequencies. For decoupling capacitors location matters hugely. Moreover, if you build and measure the real results, I propose a better method for the circuit #43. You used multiple power planes. But if you use power and ground planes interchanging from top to bottom or vice versa ( P-G-P-G) you can create a good interplanar capacitances parallel to each other. This method is said to be much better since the interplanar capacitance has very small ESL compared to chip capacitors.
this is true, but this is only partial inductance. You still have to get from the cap vias to these planes and from these planes to the ASIC or other DUT
Oh, I believe that people / articles were talking about decoupling capacitors. That is why I was so surprised. Need to find them ... PS: Good idea with the power planes. Thank you.
To me the simulation results without vias look totally fine. To my knowledge, vias have non-negligible inductance which increases the impedance at high frequencies a lot. So a direct connection is always better than vias.
how does via inductance over frequency differ from track inductance over frequency?
Great video, would love to see the real world boards tested against the simulations. Thanks
Thank you iPatroni
You demonstrate the effect of the position of the cap by showing one very far compared to one in the center. I would be curious of the result of a cap very near the power pins! Thx for the video, always fun to play the PCB version of Dora the explorer ;)
Thank you Nicolas :) PS: I am making a note about this setup.
@@RobertFeranec Yes, exactly my thought. I wonder how a single capacitor directly at the sink without vias would perform. Which is, to my knowledge, the recommended way of connecting decoupling capacities
Great Video!
If possible, I always try to place the decoupling capacitors on the same side of the IC and draw a direct connection (and not separate vias for capacitor and power pin).
In my understanding, I have two reasons:
The direct connection creates a low inductive path. That also applies for your example with a the thin, but straight direct connection. With separate vias, the current from and to the capacitor has a more odd path to follow, which results in losses for higher frequencies and impairs the decoupling effect.
The second reason is: You want to have the decoupling capacitor as the reference, not the decoupled plane around the IC. There might be still some current peaks crossing that take effect. This applies for forward and return current, so to say Power and Ground. That is why I also try to put the vias behind the decoupling capacitor, not between capacitor and IC.
this may not be a good idea. Watch for another via. The question is always the sum of the partial inductance terms. If there is a large separation between planes (say 2 layer or 4 layer PCB with symmetrical thicknesses) then the inductance of a surface trace is very high. If the two capacitor vias can be very close together, field cancellation will greatly reduce the inductance. This is in many of my lectures and bootcamps.
You are doing exactly the right thing. Keeping the noise out of the plane.
Thank you so much!
Definitely need to invite Steven and shed some light!
Thank you Zhitai. PS: Let's see how popular this video will be and how many people will ask for follow up :)
Very interesting! Especially the performance of the thin top layer traces with no vias vs. planes with vias. After some thought I would suggest that the remarkably low impedance is partially due to what the simulation is measuring. Specifically, it appears that the simulation is calculating the impedance from the S21 insertion loss parameter which measures the voltage on the output pair given a varying voltage/current on the input port. For a high speed decoupling capacitor I would think that the S22 (or S11) return loss parameter would be of greater interest which would measure how much the voltage on the output pair changes given a varying output load current. I think that the calculated impedance based on S22 would be much higher for the long skinny top layer trace case.
Thank you very much for the wonderfully informative video and keep up the great work! I would love to see some PCBs actually built and tested with a network analyzer for both S21 and S11 insertion and return loss measurements.
Robert, very nice and useful video and very surprising results! If I understand right, the loop inductance plays the main role in degrading the PDN quality. As well VIAs also degrade the loop inductance according to these results (due to their inductance). Placing decoupling capacitor far from the desired point on the board (like VCC & GND of some component) significantly reduces the influence of this capacitor on this desired area. This is the reason why it is mandatory to place as many capacitors (near all power supply pins) as possible. When we place the capacitor between two parallel traces, the travelling wave (noise) is shorted by it, and do not propagate towards the load. When this capacitor is placed far away aside, it shorts the wave propagated towards it, but not the wave propagated towards the load, and can even create travelling wave. This is how I imagine this phenomena. So, according to this video, the best way to place the decoupling capacitor is on two traces between VCC and GND vias and an appropriate componnent's pins. Please correct me if I'm wrong.
The parasitic capacitance on the example in the upper right is less since the the air is a much lower dielectric constant. Much less inductance to overcome. Results in a much lower ESR. We always use thin trace for sense lines for this reason. Good topic Robert, very well presented.
Very curious to see the real board with the real time measurements. Your videos are gem, you are really making hardware things very easy to understand. Thanks for all the effort you are putting.
Hi Robert,
I really appreciate your investigation on that topic. It made me think a lot and the following question arised: How would simulation change, if you would only connect the capacitor's power and/or ground pad directly to the IC's pads and not to the source pads. I think this case would represent a very typical design approach.
In practice, many of the "good "solutions presented in your video can't be implemented, since board area is limited. If you like to spend more time on that topic, it would be interesting to take a look on more simple/practical designs. What I mean by "simple/practical" design is:
- Place one or two capacitors of different sizes (e.g. 1u + 0.1u) really close to the IC's power pad (capacitor and IC on same board side)
- Connect the power pad of the capacitor directly to the IC's power pad with a wide trace
- Connect the power and ground pad of the capacitor to power and ground plane by via, respectively
Then you could go ahead and simulate following effects on PDN impedance:
- Number of vias connecting capacitor(s) to planes
- Position of vias relative to power/gnd pad (above, side, both)
- Via diameter / via pad size
- Capacitor orientation relative to IC edge
- Capacitor's power pad connected directly to IC vs.capacitor's power and ground pad connected directly to IC
I think this investigation is very helpful for many board designs and maybe it would be worth a short video.
From my understanding, the placement is important from loop-area standpoint but the vias also add a big problem (they're inductive mostly with capacitance to the inner plane holes). It's best to use the same layer from the capacitor to the IC power pins using very short traces (if possible) and then have the via to the power planes. This way you avoid extra inductance and you have the local decoupling with the lowest impedance to the IC (this is why you want capacitors in the first place - for high frequency transient energy).
For a more realistic simulation you should have an IBIS model of an IC with dynamic switching because the transient behaviour of an IC during switching is a non-linear current draw. The different frequencies will see different impedances due to the different current harmonics.
I had experienced your finding about cap on the same layer the hard way - EMC testing. It is all about loop area and inductance. After putting power inductors and power caps on the same side of the board, design passed EMC. With caps on the bottom we as engineers get sloppy, we forget that energy is stored in the dialectic between planes and cap plates. So if we changing plane (which we do, image current flow direction), we increase impedance a lot. I use that for filtering when I need to. If we keep decoupling cap on the same layer, we get current flow from the cap (directly between +V and GND pins of IC) on top layer, then this current is supplemented by current flow from inductive power pins. If we do not use direct connection to cap, then current flow from power plane to IC pin (through inductive vias), so voltage drop and ground bounce occur and only then additional charge comes from the cap (through inductive vias).
Very illuminating video!
25:20 I keep going back to the hydraulic analogy, because it works.Which will give you more immediate access to your local water reservoir: a long narrow tube or a short wide pipe? Of course you're going to have less impedance if the power traces are on the same layer as the capacitor; there's always going to be some additional impedance through a via, like resistance through a straw. In fact, if you plan your stackup right, you can even exploit the impedance of a via from a power plane as part of an RC decoupling filter. It's not rocket surgery, it's PCB materials engineering.
Absolutely fascinating, thank you for this! I’m definitely going to look for your other videos on this subject.
And I second the request for physical measurements to back up the simulation. My guess is the results would not be identical, but the ranking of results (which designs perform better than others) would remain the same.
I would be _very_ interested to see the load changed to a SMT connector, to simulate (or physically test) the real world case of the load being a SMT device, like a QFP or QFN device. There is debate over the best placement of decoupling capacitors in these situations, and to me your result at 23:40 makes absolute sense; there are _no_ vias between load and decoupling capacitor, and to me that would produce the lowest impedance between the two. For this reason I _always_ place SMT decoupling capacitors as close as possible to, and on the same layer as, the load device.
What I take away from this is that the two biggest factors are (1) capacitor placement as close as possible to the load, and (2) avoiding vias between capacitor and load. Then, if you _must_ via between the two, (3) maximise the number of vias in parallel, (4) maximise the number of capacitors in parallel, and (5) maximise the number of ground and power planes in parallel. Lastly, it is worth maximising trace width and minimising trace length, but after the above steps these make only marginal improvement.
Robert,
Superb post thanks so much for this.
You push everybody up to a better level.
I suspect the good result is the input and output inductance to the cap.
Thank you very much Tom
This is very good, thank you! It would be interesting to see the result when there are vias by the capacitors, and then they are connected with traces to the power pins but not the supply. That seems likely to happen in a board layout.
I always go for via in pad (with filled and capped vias) for anything that is high speed to minimise the impedance. This saves board space as well.
Excellent work, Robert! Years ago, some technical articles I read, either from Microchip or Cypress Semiconductor heavily stressed the effectiveness of placing decoupling caps near the power pins and on the same layer as the power pins of microcontrollers. EG in the case of a quad flat package. You can feed the pins their power through vias, but you want the decoupling caps between the vias and the pins. As you say, you can't always have things arranged this nice, but it's something to target when you can. I like your confirmation of surrounding power feed pins with vias improving performance. I had often suspected this would be the case. Thanks again.
You can also try X2Y caps, Three-terminal caps, reversed caps (0204, 0306 or 0508).
Thank you, Robert! Great video.
An answer to one of these every day questions developers come across.
It really helps a lot to get a better feeling what is good or bad when placing decoupling capacitors.
Thank you very much Michael
It was good to demystify the "vias on the side are better than vias on top of the pad". Very little difference indeed.
In my opinion, the interesting layout would be having the capacitor on the same side as its load connection, but the input supply coming through vias from the power planes. This is a very common implementation in DC/DC power supplies. Check the typical symmetrical CIN decoupling implementation suggested in most power devices from MPS or TI, it has minimal impedance and the EMI emitted gets canceled out by the opposite direction of the fields.
I should try this, good idea!
Yes please build these 👍 ... I'm also interested to test having the decoupling Cap before the load vs after the load 🙏
Same layer connection should win every time. Extremely small inductance in series with the capacitor compared with vias in series with the capacitor. Luckily the simulations confirmed what I guessed in that regard. Very nice job making this video 😊👍
Hi Robert, this is amazing stuff! Thank you so much! After reading so many application notes, books and following seminars on the topic, it's your videos that make it all come together in a way that is easy to follow, and you can actually *see* what happens. Even when I do indeed understand that it's a specific simulation and results may be different on a real board. Thank you for making the theory practical so that it's easier to apply in real world board design.
It would seem that the impedance - mostly inductance it seems - between the power connections and the capacitor has the most influence of how much total impedance there is at 100MHz. I see the impedance curves increasing with frequency which also seems to indicate we're looking at inductances having the most influence at those frequencies. All this time I have been thinking about how to connect *capacitors*, and now it begins to show that you may instead have to think about how to minimise *inductances* in the connections.
I was as surprised as you were at how good the one with the long thin traces and no vias was. It made me wonder about how much inductance a via really has compared to a long thin trace like that. There must be a crossover point somewhere where it's better to use vias or multiple vias than a trace. In any case, I am making a mental note to make sure my power connections are done with *wide* traces wherever I do need to use traces.
What I really wondered about is this. You placed the single capacitor right in the middle between the source and load pins. What if you placed it right next to the load pins, similar as you would do with an IC's power pins? Would you be willing to consider trying that?
A second question is how stackup comes into play here. I would assume there is a difference depending on how close the power and ground planes are in the stackup?
Thank you Christe4N. PS: Exactly the same for me - I also changed the way how I look at connecting decoupling capacitors. We may be doing follow up video with some other examples.
This debunks Rick H’s theory about placing vias in certain position. Nice job Robert! Thank you 🙏
Awesome yet again! I would love to see a video where you make the board and test it out in real life. Thanks for sharing these results!
Thank you very much Chris
I really much like this kind of videos bringing "the recipes" thar are in books or appnotes to simulations.
Good job!
Thank you very much
As usual this is pure golden :-)
I would be extremely interested in seeing the practical measurements!
Thank you so much!
Than you very much jonataubert
When it comes to decoupling, vias are inductors, so if you can, eliminate them - this is why having the cap and power plane on the same layer is so helpful. When you can't eliminate them, placing a few vias in parallel helps - up to a point - the nth via only provides 1/n improvement.
Parallel power and ground planes do add a little extra capacitance, and you can calculate how much using the area, dielectric thickness, dielectric constant, and the capacitor equation. What you will quickly figure out is that the little ceramic caps provide MUCH more capacitance than the power and ground planes, and they have a better Q.
A common problem is that the parallel power and ground planes are a much better transmission line than they are a capacitor. This means that when a slug of current gets pulled out of the planes at one spot, that voltage dip travels across the whole rest of the power/ground plane at roughly 185ps/in. So you want to make sure the chips take that current out of the decoupling cap, and NOT the power/ground plane. So make sure the power via is NOT between the chip and the cap! Otherwise, much of that current will come out of the power plane rather than the cap. A properly sized ferrite bead between the cap and the power plane can help insure that current comes out of the cap first, and what gets pulled from the plane comes out slower.
Another thing to keep in mind with the fast edge rates on modern chips, you have to consider that you don't see the whole capacitance of the entire power / ground plane pair, but only what is within the "lumped element" radius of power pin, due to the speed of currents in the PCB. This works out to roughly 0.9 inch for every nanosecond of edge time. That is, a 1ns rise time will only see a circle of about 0.9in radius of the power / ground plane pair of effective capacitance - after that it's a transmisson line.
For large chips like FPGAs, you'll want to keep in mind i = C * dv/dt. Each I/0 pin will have to drive some capacitance C at the device's rise or fall time, dv/dt. This will allow you to calculate how much current each I/O pin will source or sink when it switches state. It has to pull this current out of its associated power pin. If you have a 32-bit wide bus switching pins at the same time, then you have up to 32 times that current switching all at once. You'll be surprised at how large that current can be. Fortunately, the same equation can reconfigured to determine the size of the capacitor you need to limit dv/dt to a safe level.
Great Video again !!!
Thanks you for comparison in details ... yes I agree if we test the results with actual boards
Thank you Neeraj
Great Video - an EMC seminar once told me to run power trace across the capacitor, directly to your pin of the IC you are decoupling (Same side). So this adds up with what you have said here. Would be great to see this boards in action.
That is why I commented in previous video that it is better to have copper under component and not be worried about making a short circuit to the component :-) Wide tracks on the chip side are very important!
For smaller DC/DC converters I have around 2mm wide tracks. At 0603 capacitors one via is under the component and another is behind it. After 0603 come 1206/1210 capacitors which have multiple vias under it for both connections. Vias have 0,3mm hole with 0,5mm copper ring. If space is not a problem I have even wider track for Vcc on L1, because it forms very good capacitor with GND on the L2. Much better than capacitor between L2 and L3 in 4L board, because of less vias and smaller distance between planes.
Yes, interesting. Thank you WR3.
Very cool video.
Your last simulations are correct for the behavior of the capacitor impedance. But the split plain on the top side of the board is still a dipole. If you make it in physical boards, probe it with a near field probe to see the difference between full ground plain and split ground and power plains. I’m guessing you will measure impedance through the cap is amazing- but you still radiate with the modes of the plains.
I definitely learn something from these videos. Keep up the amazing work! Thank you.
Yes please! Much interesting and I am much curious about the actual impact of the parasitic cap-to-target (basicly direct connection vs via connection) in the real world.
As always, you have a very good approach to those kind of complex and long debated topics. Keep it up!
Thank you very much
This is stuff for the nerds... and I love it :) Please make a board for testing. Would be really interesting to see real life measurements.
Thank you very much Petatnissen :)
Hi Robert! Your video is highly informative, get to see which layout has the lowest impedance. A bit of warning for vias planting near the pads, as this would leak the solder into them, thus weakening the solder joint on the cap leads. With a weak solder joint, weak connection, bad impedance. Thank you and keep sharing!
I only recently came across this channel, but the quality is superb! Seeing results on actual boards would be fantastic, but I suggest building a few instances of one of the single cap circuits to get a sense of variation across process.
Thank you Jeremy. I am very happy some people notice how much work it is to create these videos. PS: We are working on real boards now
Excellent topic Robert, I would like to see the board builded and see it work in the real world. Thank you!
Thank you very much Edgar
Thank you Robert. I am surprised by how much difference the addition of traces makes. I would definitely like to see tests of physical boards.
Thank you very much Roger
very useful video, always wondered how the via placement on decoupling capacitors could affect its effectiveness. not very surprised for the better result on the direct connection (no vias) as I see vias as 90degree turns on a track. i hope you build these boards for real and test them, i think more surprises would come. thanks for sharing!
Thanks again @Robert,
It would be interesting to see the result for 1 capacitor close to the sink pin. As we usually do in our design. Comparison between narrow and wide traces...
Good idea for real board testing and comparison to simulation.
You rock!
Thank you very much adjada
Thanks for the comprehensive overview. Yes, please fabricate. I'm always skeptical of simulations - we'll see if it's warranted. Very valuable information as always!
Excellent video, Robert! Thank you for taking the time to do all those simulations and organizing it!
Your investigation is terrific. I would like to see the real assembly measured.
But one I would like added is say some spread of bypasses between the in/outputs, but also one at each of the input and output nodes on the same side, thus see if improvements will result from bypassing at the in and load nodes not just spread across the board. Significant is the improvements by NOT having connection by via. This is quite critical as I tend to make bypass on the direct connection to device power lines not bypass to a via to power plane near where also the device reaches power plane by a via. Hope I have made that clear what I mean
Thank you very much Helmuth. PS: That is what I would like to also try.
You should also make a poster showing all the different options from worst to best! Would be a great reference during layout to know how you might move the capacitors to optimise the PDN.
I cant wait for the altium pdn tool to include ac analysis
It could be interesting
I cannot recall where I heard this from. Someone told me that the efficiency of decoupling is all about the loop inductance (from the cap itself to the power pin). A via is an inductor as well as small traces and long distance. So a good decoupling is to minimize all 3, if you have space!
Thank you. Great video. Yes, please build the PCB. I would love to see the actual vs. simulated results comparison. Great work, Robert. I first found you back in 2012, when I was working with Altium.
That was interesting! If I understood correctly, you set the input on the left and the output on the right, so this uses capacitors as filters, not decoupling... If you set the input and output port on the same side of the pcb, it is more like the way a chip sees the impedance of the PDN at its power pin, I think you'd get different results. This would be interesting to simulate.
Definitely agree it would be interesting to compare physical measurements to simulation. Really interesting video. Thank you!
Hi Robert,
great video. Keep up the good work. I would also appreciate to see you actually build up this board and verify your simulations. That might shake up some "common PCB rules".
BTW: I always recommend your AD videos to people who are new the software. Way more efficient, than learning it by the AD manual. So, thanks for that too.
Thank you very much Sebastian
Hi Robert, great video! Really interesting. It will be amazing if you measure this!
It make sense that not using vias yield to lower impedance, because they introduce a inductance that will increase the impedance with a increase in frequency. That is why is better to use multiple vias in parallel, because you reduce the inductance (series) between the capacitor and the plane.
Greetings from Argentina!
Thank you for creating this video! This is a super useful reference for everyone that's designing PCB, especially since trace width component size and placement is difficult to understand what effects it might have on a circuit. It would be even more interesting if you built this board and did some actual measurements on it! I will definitely watch this video again the next time I'm creating a PCB, just to freshen up the memory!
Thank you very much MCUdude
Great video again, you're on a roll with EMC and SI!
Yes Build Board and Test, In the words of the Late Jim Williams, the final CAD is Copper Clad CAD!
@Robert Feranec, I’m not sure what the width of your board is, but the decoupling impedance is directly impacted by the length of the trace (including bias). So in the example of the one cap with direct connect on the top layer from PWR Supply to PWR Pin, if that total distance is less than the distance through the vias (not sure of your board thickness either, I didn’t bother converting from mm to mil), it would make perfect sense as to why you have a lower impedance.
I would have loved to see an explanation and show the correlation between your decoupling caps and the decoupling formulas. Making the math come alive would be really beneficial for us all
Great video! Your channel is a treasure chest for every EE! Almost guess them all right and funny you posted that video I was wondering about that topic!
Thank you very much Cedric
great video and very relevant to junior designers. please fabricate the boards and measure them - i'd love to learn about the instrumentation station + best practices to measure PDN
Thank you
Around 15:00 you mentioned that you had heard that decoupling cap position may not matter if you have power plane and that your sim shows that it may not be true. I would say that your power planes are really far apart and therefore ineffective. Looks like your planes are +40mils apart. If you can, run the sim again, but this time, for the stackup, keep the power planes < 8 mils. Does placement of capacitors matter then ? From literature, its that the power plane provide most of the decoupling (when < 8mils) and physical decouple caps can be much looser.
I could try this. When I was talking to Steve, he also pointed this out.
I love your scientific approach to electronics. Awesome content! Definitely, I think it's worth doing checks of the real boards. Simulations, are just simulations :) Waiting for the next video!
Thank you Jacek
Thanks Robert, fantastic work.
In terms of additional simulations to try, I would be interested to know whether it was adding more capacitors that gave you better results, or whether it was simply that by adding additional capacitors that caused some to located closer to the load terminals (on the right hand side of the board), rather than being located in the middle of the board.
Regarding using big areas of copper on the top-surface, whilst soldering the caps to big areas of copper (as in #25) gives a nice low-impedance, I suspect that the lack of thermal reliefs will cause production reliability problems during IR-reflow soldering. They would also be a nightmare for re-work, as you would have to heat up the whole copper-plane just to de-solder the capacitor. So, this might cause more trouble than it is worth.
Thank you Nicholas PS: Today, I was thinking exactly the same - if just placing some of the capacitors closer made the difference. Maybe another example to try ....
Hi Robert.
It would be interesting to compare with the installation of one low-ESL capacitor. It should be significantly better than a single conventional one at high frequencies. By shortening the track lengths and increasing the number of holes, we reduce the external inductance and hit the internal inductance limit. We can further reduce the inductance only by paralleling conventional capacitors. According to the characteristics of the capacitors, we should get the same characteristics for one low-ESL capacitor and four normal capacitors. All connected with minimum external inductance.
Congratulations again on the youtube button:)
It would also be more interesting to compare standard situations with a single capacitor and using two polygons (power and ground as in the first examples) versus a ground polygon and powering the track (in the same layer as the power polygon), via a capacitor.
Awesome one....I usually have fights and arguments with my peers on the same topic. I loved the way how simply you have explained how to analyze PDN impedance curves at 5:42....Thanks robert...looking for more high speed pcb design videos...!!
Thank you very much Gudimetla
@@RobertFeranec Hi robert, here's an video idea. Recently I started doing some RF boards for wearable devices. The entire design was alright but things started taking bad turns when coming to the RF section. The very big problem I had is to do impedance matching. I also heard this is a very big problem with lot of my hobbyist friends and makers out there as this process would need equipment like VNA's. So can you please shed some light on this topic by making a video on how to use VNA to match the impedances?( by taking a simple 50ohms boards would be enough.)
Hope you would consider the request. Would love to see a video about this on your channel.
YES you should build a few boards and measure them.
You should also add a board with single cap right next to the load pins (basically equivalen to populating the rightmost cap only on your 8 cap designs).
Hi Robert! Very interesting video as always!
If I had to justify why direct connection is better, I would say that it probably has better results because it is the shortest connection (so less inductance) and also there is no via (so shorter connection and no via parasitic inductance). Preferably use the variation with the thicker tracks or polygons.
As for the Capacitor size, I think it would make a bigger difference if we had to compare smd with through hole packages as mr.Bogatin mentioned in one of your previous videos, but maybe 0402 with 0603 for example would have little difference here at least for relatively low frequencies. Maybe it would be more noticeable for higher frequencies?
Manufacturing and measuring the real pcbs would be interesting I think.
Thank you very much giannis asp
Great content as usual,this Channel is the bible of PCB Design 🙂.
Thank you Gharbi
You seem to be in an especially good mood in this video, very pleasing to watch, thank you. I would certainly be very interested in seeing your simulation results verified by measurement, also would you consider having a look at specialty multi terminal packages like smt feedthru, x2y and lga/bga, this would be useful as most of the material available is from entities trying to sell these things
Thank you tim. It was an interesting video even for me and I was happy to see the results :)
It's very hard to track your mouse pointer with the white background, but it's ok, I can understand your point. Great video as always
Thank you Udhaya
Always enjoy your videos after a long day. This is so interesting!
Thank you Randy
I really like you man, you explain really well, thanks for your efforts to make the videos, and being funny along the way
Thank you very much Abdul
Thank you for another great explanation. These videos are invaluable. I don't know if I will ever have the chance to design something > 5MHz, but even in that domain, the conclusions are useful.
Thank you Aron
Thank you so much! And Steve!
Thickness of the core in this 4-layer stack-up is HUGE (about 1mm, like in most 4-layer stack-ups). I think that's the reason that capacitor placement appears to be more important than connection style. I would definitely reduce the distance between power and ground plane to something like 0,1mm. That is more of a "real world" value for boards where one really cares about PDN impedance.
I think this is not necessarily true. Some designs us 0.1mm, many 0.2mm-0.4mm and there are also still a lot of 4 layer PCB's
We may try different stackup in some of the other simulations.
Thank you, Robert, for this very very interesting video.
Thanks for the interesting work! I'm waiting for measurements on the pcb )
Another great video in the decoupling series. As I understand it, local decoupling (10n - 100n) needs to be at the pins, but bulk decoupling (1uF and above) just needs to be connected on the planes. It would be good to add these to your test PCB, also. It is not clear from your excellent plots how the frequency of the ESR notch is affected by the different connection types. Does this matter?
Another test would be what effect does putting the decoupling capacitor AFTER the output pins have, compared to having it BEFORE the output pins? Your test PCB from part 1 has the local decoupling after the CPU power pins, but the common advice is to make the PDN track go to the capacitor and then to the device power pins. Does this really matter?
Keep up the great work. Look forward to further involvement from Steve, Eric, and Rick!
Please build and test the PCB. Theory is important, but real measurements confirm the simulator's predictions.
P.S. I think there is more to learn about the ferrite beads from part 3.
I think thin traces with no vias achieved such a good result because You minimized prasitic inductance from vias. but when You do place one via, its better to have multiple in "parallel" because connecting inductors in parallel effectively decreases their inductance, and vias are basically small inductors.
An interesting test would be to simulate just 1 capacitor right next to the output pins on the same layer directly connected.
Is there a difference if you place 1 capacitor close to output pins, or 1 capacitor close to power pins, or 8 capacitors between? I miss this comparison in your simulations. btw. nice video ;)
Hi Juraj, From a class attended with Prof. Todd Hubing, he mentioned this aspect. You have to consider where is the power and gnd plane to decide where to place the cap. You have to think about the current flow path and consider which plane needs decoupling more (quite often the farthest plane in the stackup is where you place the decoupling cap). A usual stackup is sig, gnd,pwr,sig (im not recommending this stackup, just for eg). In this case, I would place the decoupling cap close to the power pin.
Thank you Juraj. I could try that next time. Making a note.
Very good and interesting video Robert! Great work!
Thank you Carsten
Hi Robert,
Indepth explanation. Awaiting for the real time result, I curious about know simulation tools are how close to reality!.
Jebin
Great video! It would be interesting to know how
thermal relief affects PDN.
How big is the difference between a direct connection and
through thermal relief.
As I mentioned above it depends on how big the relief is, but in general the relieve is not very significant compared to the via
Hi Robert, I think your results do make sense because of your stack up - GND and PWR are >1mm apart. Signal through the same layer traces will have less inductance/impedance than through the vias.
I would be interested to see the same simulation on closely spaced power planes (
Great video by the way.
Thanks Robert .. very interesting as always
Big thumbs up for this video, but the parallel power and ground planes on every layer are contrary to what one of your previous experts, Eric Bogatin, advocates, which is alternating power and ground planes on the PCB to minimize EMI. Would like to hear his take on this...
Re: 23:38 - the two parallel lines create another capacitor - two conductors with a dielectric between them, so it makes sense that the results are better.
Very cool. I wonder if this means that QFP / QFN parts would have an advantage over BGA devices, since it could be practical to connect the decoupling capacitors to the pins directly without vias. Although, it's likely that the reduction in inductance from the BGAs would have a larger impact.
If you have time, could you try the following configurations:
1) A T connection. Where the capacitor is directly connected to the power pin, but only connected to the power plane through vias mid-way through the connecting track (like a T where the base of the T is the via to power / gnd).
2) An L connection. Similar to the T case, you could look at the case where the via comes after the capacitor in the path (sort of like your direct connection cases, but the trace to the power input is cut and replaced with a via to the power plane instead).
I was going to suggest also placing a capacitor directly on the power output pins on the bottom layer, however, due to symmetry, you have effectively already tried that.
It would be very interesting to see if real life holds up to the simulations.
That is an interesting point. PS: I am putting the examples on my list to try
@@RobertFeranec To test the QFN/QFP vs BGA, you could probably simulate the leads via adding inductors between the connection trace and the simulation measurement points. Though you would have to find realistic values for the inductors... I did a quick search and found an app note by TI (AN-1205), which models different package leads as a RLC network - perhaps that could be helpful.
It would be nice to see the case when you connect the VCC net of the capacitor directly to the pin, but the GND is connected through vias. I think this is a pretty common scenario when designing PCBs. Would be nice to see there does it stand in the chart.
Nice video. However, since you are using a 4 layer board the spacing between power and ground planes is relatively large which makes the inductance big.
That is why your results are sensitive to capacitor placement. If you used a small spacing between power and ground plane like 3 mils then the spreading inductance would be much lower and not as sensitive to capacitor placement. Would be interesting to repeat this using 3 mil spacing.
Thank you Joel. Do you mean like this? th-cam.com/video/ELe1RNa-WC4/w-d-xo.html
@@RobertFeranec Yes, that makes perfect sense.
You are the best Robert❤
I love that your are actually simulating many different cases to try to figure out how this works, rather than just reiterating some rules of thumb that are out there.
I think your simulations are correct in some regards, but some of the conclusions might not cover the full story, so there are some further points that are worth making.
First:
You get impressive and surprising results with those long skinny traces to a capacitor between the source and load. This might at first seem surprising and I think the simulation is correct, but possibly not very relevant. I think you are simulating the shunting impedance between power and GND as it would be seen by a VNA doing an S21 measurement. So if you force the signal from port 1 to travel along arbitrarily long and skinny traces, then encounter a capacitor that shunts the power and ground trace with no parasitic inductance in the shunting other than that of the capacitor itself, the signal on the traces at the capacitor will be very effectively shorted by the capacitor (and almost all of the wave reflected back to port 1). The signal that continues towards port 2 (the load) will be very small indeed, again regardless of the length and skinny-ness of the rest of the traces.
A similar effect happens with the examples of caps connected to the planes, but either right between the source and load or far off to the side. Most of the signal from the source will go along the shortest line between the ports, and if there is a cap there, it will effectively shunt the signal. If you had had much smaller separation between the power and GND planes, you would probably see much less of this effect as the signal would spread out more due to the decreased inductance in the plane-pair
This kind of decoupling effect is relevant if you have a noisy power supply and a quiet load you want to protect form the noise. So for this case, your result that this layout is a good one is correct.
However, if the load is also noisy (draws significant current at high frequencies), this layout is no longer a good one. The impedance looking into the load terminal (as you would see if you simulated or measured the shunting impedance as seen by an S22 VNA measurement at the load) is very high due to the large inductance in the skinny traces between the port and the cap.
Most of the time (but not always) the most important purpose of a PDN is to provide clean power to loads that have noisy current consumption and thus are prone to disturb themselves. This does not seem to be the case you are simulating. To simulate this, you need to inject the signal and measure it at the same port. Or, if you want to do an S21 type of simulation, you could perhaps place port 1 on the top of the board and port 2 on the same through-hole pads, but on the bottom of the board. If you want to measure low impedances like this in the real world using a VNA, an S21 measurement from top of the board to the bottom of the board is a good setup. S11 or S22 measurements do not work very well to measure very low (or very high) impedances as they essentially need to subtract two almost identically large signals from each other and look at the difference, which is therefore extremely sensitive to small errors in the measurements of the outgoing and reflected signals.
Second:
A 4-layer board typically has a very large separation between layers 2 and 3. This is certainly true for the JLC standard stackup. This is not ideal if you want to have a low-impedance PDN on your board. So if you are stuck with a 4-layer board of this stackup and need to use layers 2 and 3 for power and GND, your conclusions about e.g. capacitors connected directly to the load is highly relevant, since there is so much inductance (and so little capacitance) in the planes, which makes it impossible to create a decoupled plane with a really low impedance.
For more advanced boards with more layers (not usually used by hobbyists, but very common in the industry), one typically strives to have a much smaller separation between the power and GND planes. 0.1 mm is rather easy and smaller separations like 0.75 mm or even 0.05 mm is not too advanced for many board shops. This totally changes the situation regarding how important it is to have decoupling caps connected directly to the pins of the load (or right between the source and the load if that is the case you are interested in).
Howard Johnson has in his black magic book a very neat and simple formula to calculate the inductance of a pair of vias connected to a pair of planes (converted to metric units):
L=mu / (2*pi) *2h * ln(2s/d)
Where:
mu/2pi = 2*10^-7 H/m
h = thickness of the dielectric
s = center separation of the vias
d = via diameter
So, the inductance is much more sensitive to the thickness of the dielectric than the via separation and via diameter, although there is some reward to be had in optimizing all of these parameters.
This formula can help estimating how important or unimportant it is to keep the vias a decoupling cap close together. The total inductance of the cap can be approximated as the one given by this formula, plus the inductance of the vias above the planes pairs, plus the inductance of the tracks between the cap and the vias, plus the inductance of the capacitor itself.
Johnson argues that this formula can also be used to estimate the inductance of a distant decoupling capacitor as seen from a load by plugging in the distance between the load and the capacitor as d in the formula. So inductance increases only logarithmically (very slowly) with increasing distance.
By the way: In multi-layer boards, there is a new factor to think of: Decoupling capacitors are more effective if they are placed on the side of the board closest to the plane-pair they are connected to, since this reduces the inductance of the vias that connect the capacitor to the planes.
Hi Robert, Something I observed also from your call with Dr. Eric Bogatin about PDN impedance is to look at impedance seen from the power port (pwr + closest GND pin) out towards the PDN network. In this simulation, is one port the input power and you are looking back from the other power port? I assume so.
I have a question about placing caps close to the power pins on QFN packages. If we keep them close, sometimes there is not enough space to put a via and then I have resorted to putting the via on the other side of the chip pin. This would be a good simulation to run as the PDN network will be seen with via and the capacitor in parallel with it.
We are looking from power pins. PS: That is an interesting example. We could try that too.
I't would have been interesting to see what kind of difference does it make if you are using thermal reliefs. I rarely use direct connection for connecting passives to power planes, that's why I'm wondering.
We can try that ... putting on my list to test
I think that for your multiple capacitor tests they might be best basically because there's at least one capacitor very near the output. I miss a test where ONE single capacitor is placed next to the output. My assumption is that this would be very good regardless of the type of connection. Also I tend to think that the smaller footprint capacitors should perform better at higher frequencies, but of course this should be tested before making a formal statement
it would be very interesting to see this test, at least for few situation (worst, best and middle)