Thank you Robert et al. I for one, find these videos very educational. I'm trying to imagine why this is happening. The ferrite bead has a higher impedance at ~60KHz because of its inductance; would a different bead affect a different frequency? Is this due to reflection between the bead and the Vcc pin? And I guess that this happens regardless of what kind of capacitors bypass at the Vcc pin? So many questions, so little brain! But thanks again.
Thank you Roger. I believe, simply to say, the peak is paralel resonance of inductance in the Bead + inductance of PCB tracks with 10uF capacitor. I recommend to watch also the previous videos - they can help to understand it.
@@RobertFeranec Hey Robert, thanks for your videos! What would happen if you would place a capacitor before the ferrite bead? I've also seen resistors used in series with capacitors to damp series resonance. Could this be used to damp parallel resonance like this as well? I've also seen small resistors used in parallel with ferrite beads. It might be interesting to simulate all of these scenarios.
@@DehimVerveen If people still will be interested in this topic, I have another videos from calls where we are making the PDN impedance graph flat. PS: There are also other ways than placing resistors in series, but yes I have seen that too. Basically, in one of the calls we remove all components from the power delivery path, you determine what capacitance and resistance you need to make it flat and then you use required number of capacitors to get that capacitance and ESR (simply to say). Another option is to keep improving what you currently have ... I have like at least two more videos, one with Eric Bogatin and one with Heidi Barnes talking on the topic how to improve it.
@@DehimVerveen It would not help because to damp resonance you need to introduce losses into the resonance circuit, this capacitor is "on the other side". What would help is an electrolytic capacitor in parallel with the 10uF or small resistor in series with the 10uF. Its ESR would serve as a parallel damping resistor. Combining ceramic caps and FB's without consideration is often problematic.
Excellent series and of considerable help to many viewers. Non comes as surprise to me, but I have near 50years in electronics behind me. Well Robert, all is in line with my general original comments made at part 1 concerning series/parralel resonances, ignoring the ferrite. But also noting the ferrite is an absorber at high frequencies, less so and inductive element except that at lower frequencies the ferrite ceases being lossy and becomes a inductance and will form its own resonant characteristics. The ferrite involved is intended to be functional at high MHz frequencies, where it is a lossy element absorbing HF passing through its zone. Sadly at these lower frequencies it is a typical high Mu device with low lisses and becomes a significant inductor and resonates. Here it was making a bad component creating serious noise. It was misused in this instance. Such ferrites should ONLY apply to very high frequency suppression or a different ferrite material with high losses in lower KHz range should be used. Given 60KHz maybe a mild iron or iron powder ferrite could have avoided the severe problem. But I would not have used the ferrite in the first place, given the frequency domain of interest.
I watched your three episodes in full. I enjoy the interactive discussions with the people you have had on. They were all very well done. Thank you for your time and the people who helped you put this together.
@@RobertFeranec I attempted to use one of the NanoVNAs to make these measurements. If you're interested, I uploaded a video of it. th-cam.com/video/Y8ouApeex78/w-d-xo.html
@@RobertFeranec I wonder if you could possibly help. I have a very simple PCB design which is nothing more than a single trace (coplanar) with a capacitor mounted in series between the two ports. I want to model the board and then remove the ground below the capacitor and compare the simulation with actual hardware. The original person who had asked about this was attempting to validate their own simulation. It seemed like an interesting experiment so I was attempting to run it for them. I looked at a free EM simulator but it dosn't support S-parameters with their EM solver. Keysight offers a trial license for ADS but I suspect it may take me that long to learn how to do anything with it. I've been watching your videos demonstrating this software and it seems it could be used for this demonstration. If you think it's something that could be done with minimal effort and you wouldn't mind helping, I would provide you with what ever information you require. You may find more details here: www.eevblog.com/forum/rf-microwave/experiment-testing-the-effects-of-releaving-ground-plane-beneth-a-component/ Thanks for your consideration.
I hope you will continue these videos. They deal with real design issues that are obviously very complicated which most designers never even consider. This particular video was very interesting (thumbs up!), but doesn't really address how to come up with an optimal design. The inductance of the ferrite bead must be interacting with a large capacitance (the bulk capacitance of the power supply?) to generate the 60 kHz resonant peak. Getting rid of the ferrite bead helps in this case, but maybe a different ferrite bead would be effective? Or maybe a small resistance (maybe 5 Ohms?) or maybe a small capacitance before the ferrite bead to generate a pi network? I have more questions after seeing the video than before! ;-) I hope in the future you will bring on some guests who will suggest how to optimize the PDN impedance curve, and then provide simulation and measurement results!
Thank you Robert for continuing this topic and deep-diving into finer details. Ferrite beads are generally good to suppress HF noise on the power lines and I generally use so many of them in all my boards, and it's surprising to see the removal of ferrite beads in fact helps to reduce impedance peaks. I personally would like to see a few more videos related to this topic and also very curious to see hardware design-related content.
Hi Robert, Thank you for these videos about this important topic! This topic is very actual in many design consideration. I've learned new perspective for considering the design of a power supply routing, and impedance calculation method. I hope, this video series will be continue soon... Regards, Balint
Hi Robert, I've watched the 3 video's in this series with great interest. I've already studied and implemented several solution myself, as they are already mentioned below . As a first note, PDN can also be simulated with Spice in AC analysis. Its not exactly the same, less accurate, but it leads to similar results and insights. A second point would be that it's a pity to throw away the ferrite bead to solve a 66kHz problem and probably risk to have an EMI problem above 100 Mhz. Simulating LC damping solutions learns that they are indeed a solution. You basically add a large capacitance (1 order of magnitude larger) with a small series resistor. The resistor can be calculated for optimal damping but it is not very critical. They usually end up in the sub 1R range. So you can sometimes use a lossy electrolytic or (not a fan myself) tantalum or a ceramic in series with a resistor. By all means, do continue to present a solution as it's very informative.
This was awesome! I’m sure this video would attract niche people who have a deeper understanding of circuit resonance and analysis and their discreet component relationship. I think those interested in RF communication would find this particularly important. For myself, learning the math and putting it into a spreadsheet (as you have done) is far cheaper and helps retain the knowledge than purchasing a high cost tool (unless you are military or telecom where speed is important). I believe this is why Eric knew in part 1 what was happening before a tool was ever used. Excellent call!
I have some other calls where we speak about it a little bit. Let's see if others are still interested about this topic and if yes, I will post it. PS: Basically, we were talking about situations, that the beads are oki for smaller currents, but may not be the best for higher currents. But I guess, the right answer if to use beads would be "it depends ..."
I'm interested for sure. I tend to add FB's to improve the chances of passing emissions testing first time, but I've never really thought that much about the downsides other than space and cost. I'd like to learn more
Robert -- yes please, do continue! This is a quite niche topic that is nonetheless valuable, and the video series will, I think, be found by viewers over a long period of time, rather than just a burst of views upon initial release.
This is both very interesting and very relevant. I'd like to filter supply side noise, as well as deliver power consistently and it seems like this is often more art than engineering. This is great content, and I hope you go even deeper with the material. It is eye opening to me. A video on how to use ferrite beads well (I don't yet see why one would be used instead of an inductor) would also be interesting.
Another great video, Thanks Robert and Florian. I really appreciate that you're covering this topic in this length and detail. I'd be very interested to see how to use ferrite beads correctly. I think I used them a bit willy nilly in the past.
Hi Robert, yes, this topic interests me very much, I was looking for a tutorial on in for a very long time and didn't find one with such in depth explanation. I am very interested to see how do you make the response flat - both "improve what you have" and "start from scratch" approaches. Another path this series could take is using LTSpice to draw and simulate PDN - using free software to achieve the same or similar results would make very good interesting content.
Thank you Robert, Florian and everyone involved. While I was still in uni I tried working out how this impedance measurement could be done and how you could use the results to get a better board. At the time I could not find the right information or people to help me. Now I finally have a bit of an idea of how these measurements are done and how you can use them. Thank you if just for that. As others have said, we have seen this particular example; but how did you or Florian find out that it was the ferrite bead? In other words: how do you interpret the results of your impedance measurements and how do you know where to start optimising your PDN, whether using different components or even changing the layout? In the case of your board, would a different bead with different impedance curve work instead? Is that even needed now? What does this mean for ferrite beads in general? Is there maybe a way you can estimate what may happen when you are still designing the schematic & layout and so make better choices for components & values when you are still designing the board? I'll be looking forward to the other videos you have planned. Thanks again Robert, this is amazing stuff!
Thanks for the video Robert. I have found the video very interesting. It is always useful to learn how to cancel high impedance to prevent any ringing when switching could create noise. I think a video explaining more in detail how to generate a PDN graph by hand would be useful, as the Bode 100 is a bit expensive.... I find sometimes problems getting my board passed for EMC on conducted emissions for instance, explaining the relation between PDN graphs and results when running a board on conducted emissions would be very very useful. Thanks again for your videos!
Hi Robert, thank you for this series that is very interesting, I learned a lot ! Considering the major undesired effect of this ferrite bead, I think it could be very nice to justify why the FB has been put in the first place :) Even though if it's only "for good practice" in that kind of case, a return to the "why is it a good practice " is always good :)
A question and a comment: 1) the FB is there to prevent noise generated by the uC from polluting the Power line and traces, to reduce conducted and radiated EMI. What are the effects of changing the FB to a Zero Ohm on the EMI of this PCB / Product? 2) This was both interesting and fascinating, BUT to paraphrase Bob Pease, my "simulator" is a soldering iron. Instead of many hours involved simulating and measuring the impedance (perhaps 5x to 10x of the actual video run time) I have many times, found a better solution in a few minutes by changing parts or the actual circuit / routing on the PCB (hint: cut out the traces and use de-soldering braid to make connections). To the commenters below about "The Ferrite Bead": There is no One Ferrite Bead, there are many, with many different characteristics, check out Murata, TDK, and others, look at the curves of the charts. PS I found you and originally watched this on Odysee
Kudos for showing a painful/embarrassing learning process in public! When I first started this video, I was pulling my hair out seeing that ferrite bead in series with a digital chip’s Vcc pin, NO NO NO! I was shouting at you. In 3 hours of these 3 videos, you’ve taught even better what I too learned by attending one of Rick Hartley’s workshops on this topic at PCB West several years ago, and in about the same amount of time! lol. Do you remember where it was you ‘learned’ to put ferrite beads in series with digital chip’s Vcc pins? I see it a lot, and now that I know better, I wonder where it’s coming from…?
@@RobertFeranec Ahhhh. I vividly remember in Rick Hartley's workshops him quoting one of the other 'EMC gurus' (Henry Ott? Todd Hubing? I can't remember now), "Datasheets and especially App-Notes should be considered wrong, until proven right!". Sometimes these documents are written by "the new guy", the least experienced &/or newly hired engineers in these semi companies :-(
That was a great set of videos. I would like to see more of Eric's calculation of the impedance of the Vcc. Do you have another video with Eric do this calculation? And is there a way of finding, may be by some ruff calculation, what's going on without a VNA or expensive software?
Thanks a lot! It brings light to some question I was trying to answer about ringing. Please, continue with these power integrity topics, aspecially regarding proper use of beads) Maybe, show same application cases in power electronics (converters), with routing examples. Anyway, it`s great topic!
I'd love to know what capacitance is required to kill that other spike you are seeing in the graph between the 1uF and 0.1uF dips.. It looks like a 0.47uF cap would probably do the trick, but improving the capacitor layout and capacitor value selection would be an extremely interesting addition to this topic
Great video - really enjoyed it. I had a few queries: 1. Why was there a ringing observed at roughly 1.3KHz? 2. The main objective of decoupling with multiple caps is to avoid any PDN impedance peaking upto the maximum switching frequency (with some guardband)? 3. Could you post your full video call with Eric?
Great Robert, I like your video because there are a lot of practical tips. I knew this topic in theory but if we can do some measures the "music changes" and we can do better products.
Hi Robert - I appreciate the background and science behind the results but you have left more questions than you have answered in your 3 videos? Engineers use ferrite beads according to manufacturers recommendations but you have shown that parallel impedances caused by ferrite beads can be a problem at some frequencies? The question should be what decoupling strategy is appropriate for the frequencies being used by the device? How can we optimise the decoupling strategy to give the best results for the appropriate frequency? CAD engineers need a simple set of guidelines to optimise layout when presented with a challenge to meet the engineers schematic requirements.
Great video - more please! I'm interested in core-rail power integrity for boards with accelerator chips, which produce difficult transient-currents. These loads are packaged in large, small-pitch BGAs, which inevitably leads to perforation of power planes. The sharp transients can repeat at frequencies within the VRM loop bandwidths, which means that it's unclear that the power-supply and the PDN can be analysed separately. Concerning ferrite beads, I often see recommendations to use them on the power pins of sensitive interfaces such as PCIe, but it's not clear to me that this is always a good idea, as series inductance can be a problem. Thanks!
I just want to say thank you for this video. It is very informative and helpful in understanding what issues may be responsible for noise in the pcb layout - I enjoyed it very much! Question: I noticed Florian used a capacitor between the circuit board and the Bode 100 to block the dc signal from circuit board to prevent interference. This, however, influenced the overall impedance. Can a blocking diode be used instead to do the same thing? e.g., a Schottky type with low forward voltage.
Really nice series of video, should be very interesting for me to see also which is the effect of different ferrite beads values. Also "see in action" the filter effect and then without filter in terms of noise reduction that can come from power supply and that could be injected into.
@@RobertFeranec No worries, thinking about a good future video would be how you import and test a board from Altium Designer into the Keysight SI software
Hey Robert, thanks for your videos! I don't understand, which steps make did Florian for will better return noise when has controller signals are pulsed. May was it calculated optimate a type or nominal value of capacitors and did it? Very intresting!
Perfect but. now how to use ferrites? On one of your videos Eric told: it's for designing filters. I think power filter, since we evaded use resistor to prevent power loss on DC. But how to design that. You explained how to design filter for EMI and EMC with low inductance inductor using special logarithmic paper. But how design filters with ferrite beads?
Robert, thank you for great series of video series watched four times..🙏 Niose generating ferrite bead?? 🤯 I am wondering, microcontroller or microprocessor's frequency will generate noise on supply rail/ground? f=clock or f=clock*scaler?
Very interesting and great video, now it's more clear to me about decoupling and PDN simulation! Altium has PDN analyzer, do you think it's effective as Keysight ADS??
Altium PDN Analyzer calculates PCB currents and voltages at DC only. Hopefully they will add AC analysis, like the tools used here. It is a useful tool, but for resistance, not impedance vs frequency. 🙁
Hello Robert! Thank you for this usefull video. I see after replacing the FB with a 0 Ohm resistor the noise is gone at VCC pin but the voltage on VCC pin is also gone, it's practically 0V on Channel 1. I don't understand how your IC was working without power on the VCC pin.
Thank you very much for the video. But interestingly I have the impression that the FB has worse effects than good. Can we way that we should not place a FB at the output of the power supply?
Yes, the BEAD in this case may not be the best. PS: BEAD still can be used in power, but ideally only in places with small currents. For bigger currents it can be a problem.
I'm not an engineer, but I saw all your videos about decoupling and also I saw the video about pdn impedance. But I don't understand why you don't want more impedance while the frequency increase to have a near real DC voltage to feed the chip. It doesn't make sense for me to let pass the high frequency to feed chips. I read almost all the comments and I didn't see anyone who pointing out this, so I'm sure that I didn't understand very well the goal to let pass all the frequency. Could Someone explain me ? Thanks from a Belgian guy.
Hi what if the controller/processors IO switching frequency is much higher like 400 or 500MHz can I still use this Bode100 to measure the pdn impedance?
It will be explained in next videos, but very simple answer is, that anything above 100-300MHz is influenced in connection on the chip itself (because of inductance and capacitance in the chip)
As usual a great video. I was searching myself about this ferrite bead issue. And I found a very good application note about it. I am still going through it. I don't know if you have already gone it or not, but if you haven't www.analog.com/media/en/technical-documentation/application-notes/AN-1368.pdf this is the link for it. Please have a look at it everyone and enjoy!
make ads setup videos. Also same analysis for a 100mhz datarate or something high verifying performance with same technique and hoow to adjust the traces for best performance
In future I will be more careful when using ferrite beads. Always good to really understand. I recommend the following article for very useful information about ferrite beads and damping solutions: www.analog.com/en/analog-dialogue/articles/ferrite-beads-demystified.html
Thank you Robert et al. I for one, find these videos very educational. I'm trying to imagine why this is happening. The ferrite bead has a higher impedance at ~60KHz because of its inductance; would a different bead affect a different frequency? Is this due to reflection between the bead and the Vcc pin? And I guess that this happens regardless of what kind of capacitors bypass at the Vcc pin? So many questions, so little brain! But thanks again.
Thank you Roger. I believe, simply to say, the peak is paralel resonance of inductance in the Bead + inductance of PCB tracks with 10uF capacitor. I recommend to watch also the previous videos - they can help to understand it.
@@RobertFeranec Hey Robert, thanks for your videos! What would happen if you would place a capacitor before the ferrite bead? I've also seen resistors used in series with capacitors to damp series resonance. Could this be used to damp parallel resonance like this as well? I've also seen small resistors used in parallel with ferrite beads. It might be interesting to simulate all of these scenarios.
@@DehimVerveen If people still will be interested in this topic, I have another videos from calls where we are making the PDN impedance graph flat. PS: There are also other ways than placing resistors in series, but yes I have seen that too. Basically, in one of the calls we remove all components from the power delivery path, you determine what capacitance and resistance you need to make it flat and then you use required number of capacitors to get that capacitance and ESR (simply to say). Another option is to keep improving what you currently have ... I have like at least two more videos, one with Eric Bogatin and one with Heidi Barnes talking on the topic how to improve it.
@@RobertFeranec That sounds very interesting. I know I would definitely watch that!
@@DehimVerveen It would not help because to damp resonance you need to introduce losses into the resonance circuit, this capacitor is "on the other side". What would help is an electrolytic capacitor in parallel with the 10uF or small resistor in series with the 10uF. Its ESR would serve as a parallel damping resistor. Combining ceramic caps and FB's without consideration is often problematic.
Excellent series and of considerable help to many viewers. Non comes as surprise to me, but I have near 50years in electronics behind me.
Well Robert, all is in line with my general original comments made at part 1 concerning series/parralel resonances, ignoring the ferrite. But also noting the ferrite is an absorber at high frequencies, less so and inductive element except that at lower frequencies the ferrite ceases being lossy and becomes a inductance and will form its own resonant characteristics.
The ferrite involved is intended to be functional at high MHz frequencies, where it is a lossy element absorbing HF passing through its zone. Sadly at these lower frequencies it is a typical high Mu device with low lisses and becomes a significant inductor and resonates. Here it was making a bad component creating serious noise. It was misused in this instance. Such ferrites should ONLY apply to very high frequency suppression or a different ferrite material with high losses in lower KHz range should be used. Given 60KHz maybe a mild iron or iron powder ferrite could have avoided the severe problem. But I would not have used the ferrite in the first place, given the frequency domain of interest.
I watched your three episodes in full. I enjoy the interactive discussions with the people you have had on. They were all very well done. Thank you for your time and the people who helped you put this together.
Thank you very much joe
@@RobertFeranec I attempted to use one of the NanoVNAs to make these measurements. If you're interested, I uploaded a video of it. th-cam.com/video/Y8ouApeex78/w-d-xo.html
@@joesmith-je3tq Nice!
@@RobertFeranec I wonder if you could possibly help. I have a very simple PCB design which is nothing more than a single trace (coplanar) with a capacitor mounted in series between the two ports. I want to model the board and then remove the ground below the capacitor and compare the simulation with actual hardware. The original person who had asked about this was attempting to validate their own simulation. It seemed like an interesting experiment so I was attempting to run it for them. I looked at a free EM simulator but it dosn't support S-parameters with their EM solver.
Keysight offers a trial license for ADS but I suspect it may take me that long to learn how to do anything with it. I've been watching your videos demonstrating this software and it seems it could be used for this demonstration. If you think it's something that could be done with minimal effort and you wouldn't mind helping, I would provide you with what ever information you require. You may find more details here:
www.eevblog.com/forum/rf-microwave/experiment-testing-the-effects-of-releaving-ground-plane-beneth-a-component/
Thanks for your consideration.
I hope you will continue these videos. They deal with real design issues that are obviously very complicated which most designers never even consider.
This particular video was very interesting (thumbs up!), but doesn't really address how to come up with an optimal design. The inductance of the ferrite bead must be interacting with a large capacitance (the bulk capacitance of the power supply?) to generate the 60 kHz resonant peak. Getting rid of the ferrite bead helps in this case, but maybe a different ferrite bead would be effective? Or maybe a small resistance (maybe 5 Ohms?) or maybe a small capacitance before the ferrite bead to generate a pi network? I have more questions after seeing the video than before! ;-)
I hope in the future you will bring on some guests who will suggest how to optimize the PDN impedance curve, and then provide simulation and measurement results!
Thank you ats89117 PS: my plan is, that the other videos would be explaining how to optimize it (I already have some calls recorded)
@@RobertFeranec That would be very interesting to see what is your approach to flatten the curve!
You should definitely continue these series, these were great!!! and I hope you keep continuing this topic.
Thank you Robert for continuing this topic and deep-diving into finer details. Ferrite beads are generally good to suppress HF noise on the power lines and I generally use so many of them in all my boards, and it's surprising to see the removal of ferrite beads in fact helps to reduce impedance peaks. I personally would like to see a few more videos related to this topic and also very curious to see hardware design-related content.
Hi Robert,
Thank you for these videos about this important topic!
This topic is very actual in many design consideration. I've learned new perspective for considering the design of a power supply routing, and impedance calculation method.
I hope, this video series will be continue soon...
Regards,
Balint
Yes, please continue! Even past ep 4 which has already been released
Hi Robert, I've watched the 3 video's in this series with great interest. I've already studied and implemented several solution myself, as they are already mentioned below . As a first note, PDN can also be simulated with Spice in AC analysis. Its not exactly the same, less accurate, but it leads to similar results and insights. A second point would be that it's a pity to throw away the ferrite bead to solve a 66kHz problem and probably risk to have an EMI problem above 100 Mhz. Simulating LC damping solutions learns that they are indeed a solution. You basically add a large capacitance (1 order of magnitude larger) with a small series resistor. The resistor can be calculated for optimal damping but it is not very critical. They usually end up in the sub 1R range. So you can sometimes use a lossy electrolytic or (not a fan myself) tantalum or a ceramic in series with a resistor.
By all means, do continue to present a solution as it's very informative.
"PDN can also be simulated with Spice in AC analysis" thats interesting , how have you done that ?
This was awesome! I’m sure this video would attract niche people who have a deeper understanding of circuit resonance and analysis and their discreet component relationship. I think those interested in RF communication would find this particularly important. For myself, learning the math and putting it into a spreadsheet (as you have done) is far cheaper and helps retain the knowledge than purchasing a high cost tool (unless you are military or telecom where speed is important). I believe this is why Eric knew in part 1 what was happening before a tool was ever used. Excellent call!
Thank you very much Code Designs for watching number of my videos and also for leaving comments. I read them all.
@@RobertFeranec Thank you for the amazing videos and very informative content! Keep up the excellent work! You are a great teacher/engineer!
I would like to know more about the ferrite beads. If it's a good practice or bad practice and so on.
I have some other calls where we speak about it a little bit. Let's see if others are still interested about this topic and if yes, I will post it. PS: Basically, we were talking about situations, that the beads are oki for smaller currents, but may not be the best for higher currents. But I guess, the right answer if to use beads would be "it depends ..."
I'm interested for sure. I tend to add FB's to improve the chances of passing emissions testing first time, but I've never really thought that much about the downsides other than space and cost. I'd like to learn more
I would also like to know more about when to use beads and when not - I know it is not a simple question to answer:)
Thanks so much Robert . I’ll look forward to watching this after work today 🙏
Thank you Adam
That's a really good practical demo of their product, definitely gonna try to do a similar measurement in my next board.
Thank you Genghisnico13 PS: I am thinking exactly the same, I am now curious to see how PDN impedance would look for some of our boards.
Robert -- yes please, do continue! This is a quite niche topic that is nonetheless valuable, and the video series will, I think, be found by viewers over a long period of time, rather than just a burst of views upon initial release.
Thank you very much Graham
I'm still VERY interested!!! Thank you Robert for this series!
Thank you guillep2k
Fantastic series an decoupling and desing. Very well explained. Thank you Robert for the time and effort. Be safe!
Thank you very much Edgar
This is both very interesting and very relevant. I'd like to filter supply side noise, as well as deliver power consistently and it seems like this is often more art than engineering. This is great content, and I hope you go even deeper with the material. It is eye opening to me.
A video on how to use ferrite beads well (I don't yet see why one would be used instead of an inductor) would also be interesting.
Another great video, Thanks Robert and Florian. I really appreciate that you're covering this topic in this length and detail. I'd be very interested to see how to use ferrite beads correctly. I think I used them a bit willy nilly in the past.
Thank you very much PS: I have used a lot of beads, now I am going to be much more careful ....
Hi Robert, yes, this topic interests me very much, I was looking for a tutorial on in for a very long time and didn't find one with such in depth explanation. I am very interested to see how do you make the response flat - both "improve what you have" and "start from scratch" approaches.
Another path this series could take is using LTSpice to draw and simulate PDN - using free software to achieve the same or similar results would make very good interesting content.
Thank you very much miceuz
Would be interesting to do the impedance measurement with a "red pitaya"!
Thank you Robert, Florian and everyone involved. While I was still in uni I tried working out how this impedance measurement could be done and how you could use the results to get a better board. At the time I could not find the right information or people to help me. Now I finally have a bit of an idea of how these measurements are done and how you can use them. Thank you if just for that.
As others have said, we have seen this particular example; but how did you or Florian find out that it was the ferrite bead? In other words: how do you interpret the results of your impedance measurements and how do you know where to start optimising your PDN, whether using different components or even changing the layout?
In the case of your board, would a different bead with different impedance curve work instead? Is that even needed now? What does this mean for ferrite beads in general?
Is there maybe a way you can estimate what may happen when you are still designing the schematic & layout and so make better choices for components & values when you are still designing the board?
I'll be looking forward to the other videos you have planned. Thanks again Robert, this is amazing stuff!
Thanks for the video Robert. I have found the video very interesting. It is always useful to learn how to cancel high impedance to prevent any ringing when switching could create noise. I think a video explaining more in detail how to generate a PDN graph by hand would be useful, as the Bode 100 is a bit expensive.... I find sometimes problems getting my board passed for EMC on conducted emissions for instance, explaining the relation between PDN graphs and results when running a board on conducted emissions would be very very useful. Thanks again for your videos!
Thank you Daniel.
Very good series Robert! Very important and interesting topic!
Thanks for the high quality content in all your videos! Keep up!
Thank you very much giannis
Hi Robert, thank you for this series that is very interesting, I learned a lot !
Considering the major undesired effect of this ferrite bead, I think it could be very nice to justify why the FB has been put in the first place :) Even though if it's only "for good practice" in that kind of case, a return to the "why is it a good practice " is always good :)
A question and a comment:
1) the FB is there to prevent noise generated by the uC from polluting the Power line and traces, to reduce conducted and radiated EMI. What are the effects of changing the FB to a Zero Ohm on the EMI of this PCB / Product?
2) This was both interesting and fascinating, BUT to paraphrase Bob Pease, my "simulator" is a soldering iron. Instead of many hours involved simulating and measuring the impedance (perhaps 5x to 10x of the actual video run time) I have many times, found a better solution in a few minutes by changing parts or the actual circuit / routing on the PCB (hint: cut out the traces and use de-soldering braid to make connections).
To the commenters below about "The Ferrite Bead": There is no One Ferrite Bead, there are many, with many different characteristics, check out Murata, TDK, and others, look at the curves of the charts.
PS I found you and originally watched this on Odysee
This video has been very interesting too. Please do next video.
Kudos for showing a painful/embarrassing learning process in public! When I first started this video, I was pulling my hair out seeing that ferrite bead in series with a digital chip’s Vcc pin, NO NO NO! I was shouting at you. In 3 hours of these 3 videos, you’ve taught even better what I too learned by attending one of Rick Hartley’s workshops on this topic at PCB West several years ago, and in about the same amount of time! lol. Do you remember where it was you ‘learned’ to put ferrite beads in series with digital chip’s Vcc pins? I see it a lot, and now that I know better, I wonder where it’s coming from…?
for some years, It was in many reference designs
@@RobertFeranec Ahhhh. I vividly remember in Rick Hartley's workshops him quoting one of the other 'EMC gurus' (Henry Ott? Todd Hubing? I can't remember now), "Datasheets and especially App-Notes should be considered wrong, until proven right!". Sometimes these documents are written by "the new guy", the least experienced &/or newly hired engineers in these semi companies :-(
@Robert Thanks for this video! I would love to see what else you have on this subject. This has been a very informative series. Keep it going.
Thank you for the video! I wonder, would it be possible to perform such/similar measurement using a miniVNA?
Very informative video. Pls continue with more videos on this topic. Thanks
Thank you very much Rajat
That was a great set of videos.
I would like to see more of Eric's calculation of the impedance of the Vcc. Do you have another video with Eric do this calculation?
And is there a way of finding, may be by some ruff calculation, what's going on without a VNA or expensive software?
Go ahead with this topic! Very nice!
Thanks a lot! It brings light to some question I was trying to answer about ringing. Please, continue with these power integrity topics, aspecially regarding proper use of beads) Maybe, show same application cases in power electronics (converters), with routing examples. Anyway, it`s great topic!
Thank you very much Peter
I'd love to know what capacitance is required to kill that other spike you are seeing in the graph between the 1uF and 0.1uF dips.. It looks like a 0.47uF cap would probably do the trick, but improving the capacitor layout and capacitor value selection would be an extremely interesting addition to this topic
Great video - really enjoyed it. I had a few queries:
1. Why was there a ringing observed at roughly 1.3KHz?
2. The main objective of decoupling with multiple caps is to avoid any PDN impedance peaking upto the maximum switching frequency (with some guardband)?
3. Could you post your full video call with Eric?
Great Robert, I like your video because there are a lot of practical tips. I knew this topic in theory but if we can do some measures the "music changes" and we can do better products.
Hi Robert - I appreciate the background and science behind the results but you have left more questions than you have answered in your 3 videos? Engineers use ferrite beads according to manufacturers recommendations but you have shown that parallel impedances caused by ferrite beads can be a problem at some frequencies? The question should be what decoupling strategy is appropriate for the frequencies being used by the device? How can we optimise the decoupling strategy to give the best results for the appropriate frequency? CAD engineers need a simple set of guidelines to optimise layout when presented with a challenge to meet the engineers schematic requirements.
Great video - more please! I'm interested in core-rail power integrity for boards with accelerator chips, which produce difficult transient-currents. These loads are packaged in large, small-pitch BGAs, which inevitably leads to perforation of power planes. The sharp transients can repeat at frequencies within the VRM loop bandwidths, which means that it's unclear that the power-supply and the PDN can be analysed separately. Concerning ferrite beads, I often see recommendations to use them on the power pins of sensitive interfaces such as PCIe, but it's not clear to me that this is always a good idea, as series inductance can be a problem. Thanks!
I just want to say thank you for this video. It is very informative and helpful in understanding what issues may be responsible for noise in the pcb layout - I enjoyed it very much!
Question:
I noticed Florian used a capacitor between the circuit board and the Bode 100 to block the dc signal from circuit board to prevent interference. This, however, influenced the overall impedance.
Can a blocking diode be used instead to do the same thing? e.g., a Schottky type with low forward voltage.
Really nice series of video, should be very interesting for me to see also which is the effect of different ferrite beads values. Also "see in action" the filter effect and then without filter in terms of noise reduction that can come from power supply and that could be injected into.
Thank you Luca
Please do more of this topic
Very interesting subject definitely keep more coming, thank you
Thank you very much
@@RobertFeranec No worries, thinking about a good future video would be how you import and test a board from Altium Designer into the Keysight SI software
Hey Robert, thanks for your videos! I don't understand, which steps make did Florian for will better return noise when has controller signals are pulsed. May was it calculated optimate a type or nominal value of capacitors and did it? Very intresting!
Excellent video..!! I would like to know, how the absence of the ferrite core impacted the high frequency filtering. If there is a part 4. Haha.
Perfect but. now how to use ferrites? On one of your videos Eric told: it's for designing filters. I think power filter, since we evaded use resistor to prevent power loss on DC. But how to design that. You explained how to design filter for EMI and EMC with low inductance inductor using special logarithmic paper. But how design filters with ferrite beads?
Robert, thank you for great series of video series watched four times..🙏 Niose generating ferrite bead?? 🤯 I am wondering, microcontroller or microprocessor's frequency will generate noise on supply rail/ground? f=clock or f=clock*scaler?
Very interesting and great video, now it's more clear to me about decoupling and PDN simulation! Altium has PDN analyzer, do you think it's effective as Keysight ADS??
Thank you Anas PS: I am thinking to have a look at Altium's PDN analyzer
Altium PDN Analyzer calculates PCB currents and voltages at DC only. Hopefully they will add AC analysis, like the tools used here. It is a useful tool, but for resistance, not impedance vs frequency.
🙁
@@robertdixon8238 In that case it's not support Switching Mode Power supply Network!?
Anas Albaidhani It can be used to analyse DC paths of a switching supply, only. It does not compute the Bode plot, as shown in the tools here.
@@robertdixon8238 ok thanks Robert
Hello Robert! Thank you for this usefull video. I see after replacing the FB with a 0 Ohm resistor the noise is gone at VCC pin but the voltage on VCC pin is also gone, it's practically 0V on Channel 1. I don't understand how your IC was working without power on the VCC pin.
The scope is set to show AC only, so you will not see DC value.
Your last step: manipulate your PDN so you match the impedance of your load to the source😉.
Signed, RF engineer
:)
You deserve more subscribers.
Thank you very much rasher
Thanks for video! This information is very helpful for similar situations with power rails... :)
Thank you Arturs
Thanks Robert! Awesome video .
Thank you very much Sudheer
excellent video..!!
Thank you very much for the video. But interestingly I have the impression that the FB has worse effects than good.
Can we way that we should not place a FB at the output of the power supply?
Yes, the BEAD in this case may not be the best. PS: BEAD still can be used in power, but ideally only in places with small currents. For bigger currents it can be a problem.
Hmm I see, thank you very much for the information.
Eric Bogatin mentions something called Target Impedance of PDN. However, I did not see it mentioned anywhere in this video.
Can you please measure the frequency response of FB in the next videos to find out why it behaves like this in this frequency?
I wonder if there is a cheaper way to measure PDN impedance.
Thank you so much Robert, I like you very much :)
Very interesting video!
Thank you very much Santi
I'm not an engineer, but I saw all your videos about decoupling and also I saw the video about pdn impedance. But I don't understand why you don't want more impedance while the frequency increase to have a near real DC voltage to feed the chip. It doesn't make sense for me to let pass the high frequency to feed chips. I read almost all the comments and I didn't see anyone who pointing out this, so I'm sure that I didn't understand very well the goal to let pass all the frequency.
Could Someone explain me ?
Thanks from a Belgian guy.
why NanoVNA F ,etc could not do the job here? 50khz to 1ghz, could be more interesting?
Nice video, TNX
It is aSFRA kit from Omicron?
It is BODE 100 from Omicron
Hi what if the controller/processors IO switching frequency is much higher like 400 or 500MHz can I still use this Bode100 to measure the pdn impedance?
It will be explained in next videos, but very simple answer is, that anything above 100-300MHz is influenced in connection on the chip itself (because of inductance and capacitance in the chip)
I dont see how you fix the differences between simulation and measurement shows at 34:35?
Why the PDN impedance is lower when VCC is on?
Do you mean at the beginning? I believe, that is simply caused by power supply being powered and working
Thank u
As usual a great video. I was searching myself about this ferrite bead issue. And I found a very good application note about it. I am still going through it. I don't know if you have already gone it or not, but if you haven't
www.analog.com/media/en/technical-documentation/application-notes/AN-1368.pdf
this is the link for it. Please have a look at it everyone and enjoy!
Mmmmmm, very interesting ! Thank you Robert
Thank you very much adjada
make ads setup videos. Also same analysis for a 100mhz datarate or something high verifying performance with same technique and hoow to adjust the traces for best performance
In future I will be more careful when using ferrite beads.
Always good to really understand.
I recommend the following article for very useful information about ferrite beads and damping solutions:
www.analog.com/en/analog-dialogue/articles/ferrite-beads-demystified.html
I find the term "peak" very relative. Yes it's a peak, but it's still a lot lower without decoupling.
:) PS: Thank you P_Mouse for watching
There are cat videos? Who knew.
:D
Yep, there are network guys posting very interesting vlogs about Cat5, Cat5e, Cat6... etc :-)
@@Graham_Wideman :D