Introduction to FPGA Part 10 - Metastability and Clock Domain Crossing | Digi-Key Electronics
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- เผยแพร่เมื่อ 28 ส.ค. 2024
- A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.
In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).
Previously, we showed how to use a phase-locked loop (PLL) to increase clock speed as well as introduced the concept of glitches. In this episode, we examine how setup and hold time violations can cause metastability in flip-flops.
The solution to the challenge at the end of the episode can be found here: www.digikey.co...
All code examples and solutions for this series can be found here: github.com/Sha...
Colin O’Flynn’s metastability experiment: colinoflynn.co...
Better clock divider example: github.com/Sha...
Better button debounce design: github.com/Sha...
Clifford Cummings’s FIFO paper: www.sunburst-de...
A flip-flop requires the input signal to be steady for some time before the clock edge (setup time) and remain steady for some time after the clock edge (hold time). If the input signal transitions during the setup or hold windows, then it is considered a timing violation. This could potentially cause metastability on the flip-flop, where the output remains in an unknown state for some indeterminate amount of time.
Normally, the metastable output will settle on logic high or logic low quickly (within a few nanoseconds), but it is not guaranteed. Metastable events can cause potentially catastrophic failures in a design and can be very difficult to track down due to their probabilistic nature.
The standard fix to mitigate the likelihood and impact of metastability is to use a synchronizer circuit, which consists of 2 or more flip-flops chained together. The input of one flip-flop samples the output of another. Note that this introduces an extra clock cycle of delay for each flip-flop you put in the chain.
A first-in, first-out (FIFO) system is one way to pass data from one class domain to another. Elements are read from the FIFO in the order in which they were written. We can use dual-port block RAM to construct a FIFO in our iCE40. Your challenge is to implement Clifford Cummings’s FIFO design and test it via simulation.
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This series impressively well-conceived and well executed. I have found many gems and overall find the series to be genuinely practical and directly useful. Many thanks.
Can I ask if possible you make this a longer series and delve into the more complex areas of FPGAs and digital design. Your tutorials are very well made and very informative and you explain things in a very easy to understand way.
really amazing. very clear presentation. everyone who is starting out should watch this. even people who know HDL should give it a watch. thank you.
I'm having problem related to clock rn, you came just in time Shawn!
Great video - nice work Shawn!
Great stuff. Really covering all the important topics. Keep going.
Another great entry to this series!
You should also have probably mentioned that many of the bigger vendors have built-in FIFO logic with their block RAMs (i.e. Intel and Xilinx). You're always better off using the built-in logic (unless there is a special need to not use it - such as reducing delay). The downside though, is that those FIFOs are not inferable and instead need to be instantiated via macro. Often the solution to make a design cross-platform is to wrap the FIFO implementation in a generic module, and include the relevant implementation for the given target (even across Xilinx chips for example, there is a different macro for the 6 series, 7 series, and Ultrascale series).
FIFOs can also be used to pass generic control signals other than pure data. One method is to do delta-compression, where only bit-vector updates are pushed to the FIFO (so you encode the signal bit-vector with XOR when you push, and decode it with XOR when you pull. If you didn't do that and instead pushed every clock pulse, then you could easily overrun the FIFO). If you need bi-directional signals, you can use two FIFOs in either direction. One easy example where this is very useful, is VGA timings. If you have a VGA output driver (with variable clock and timing for different monitor resolutions), and a set frequency image generator (like a bitmap BLITer), you can use a FIFO to send synchronization signals such as "Start_of_frame", and "new_scanline", to keep the image generator in sync with a scanline buffer (that allows you to use a scanline buffer instead of a full frame-buffer).
The only times I have ever used a synchronizer, where cases where the update can be fuzzy (i.e. glitching is acceptable). And doing so requires specialized timing constraints to prevent the P&R tool from complaining about timing violations (usually I use a false-path constraint, which will stochastically add delay to the synchronizer making it completely impractical for general clock domain crossing).
Anyway, looking forward to the next episode!
I am so eager to run through this series myself starting from the beginning tutorial however I can't start without a board. Sorry if you have already addressed this a hundred times but I am guessing that until the chip shortage is over (in 3 years :)) we will just have to hang tight.
Thank you 👍
Everything good but you didn't explain how a synchronizer works. That's what I was searching for in the whole video but then it jumped to FIFO fsr.
Using an asynchronous reset is also discouraged. You should only have a single process that converts your asynchronous reset to synchronous. The rest of your logic should run on the synchronous reset.
Good point, thanks! I've seen some chips that are fine with asynchronous reset, but I do agree that it makes more sense to use synchronous resets where possible.
@@ShawnHymel it helps most to assure that multiple circuits come out of reset at the same time.
This is a big issue with high precision sensors, because you don't want sensor modulation frequencies to be harmonically synchronous with your demodulation system. So you have to decouple the two systems, and pass data between them asynchronously.