I feel that the input to second flipflop(=FF2) is always 0 when reset was applied and it will be constant (not changing right before reset asserted or clk edge) and that is why FF2 output will never be metastable
@@kamleshraiter658 if we look at the scenario before reset gets deasserted, input of FF1 is tied to logic 1 and output is 0, but in case of FF2, the input is 0 and the output is also 0. So there will be logic differential for FF1 once reset is deasserted in reset recovery time and output will oscillate i.e metastable.But not for FF2 as there is no logic differential. This is my understading. pls correct me if anything is ambiguous in my coclusion
Hello Ashmika, I think, I created it long back. Even I could not find it because its title is different. BTW, I will create a new one on your suggestion.
I have a question, Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
if you are talking about dual flop synchronizer for data.. it depends upon your design architecture expectations. But w.r.t metastability, I dont think it will cause any issue. if you are facing any issue, let me know we can discuss.
@@TechnicalBytes Hi, thank you for your reponse. I managed to fix it. The problem was not with the clock gating. I have another question, if you could help me: I'm using a handshake synchronizer, and I have control signals of it (Ack and Req). It is used in my FSM to control the data sent in one domain to another. However, the tool says that it is a convergence of signals (control signals synchronized combined in a logic). Do you know where I can find more informations if I should waive this problem or find another solution to avoid convergence of control signals of handshake synchronizer?
Since 2nd flip flop will sample after 1 cycle delay the input data would be stable but still if metastability of 1st FF makes output 0 instead of 1 or vice versa then even 2nd FF can go metastable . Please give your feedback regarding my answer
Assume there is a flop F1 clocked by a clock signal, say clk1. We say this flop is in clk1 clock domain(or clock boundary, any other flops having clk1 as clock would be a part of the same clk1 clock domain). Another flop F2 clocked by a different flop, say clk2 is present in some other part of the design. If we need to send some input data signal to F2 from F1, this signal would cross(move) from clk1 domain to clk2 domain as the destination flop F2 is of clk2 domain. This incoming signal from F1 appears as asynchronous to the F2 flop as it is from a different clock domain and this may lead to metastability. We can say that the input signal has crossed clock boundaries/domains (from clk1 to clk2) which is pretty much what a clock domain crossing (CDC) is.
Reset syncronizer is used for asyn reset which clearly means whenever I will assert my reset it should get applied immediately.
you are right.
I feel that the input to second flipflop(=FF2) is always 0 when reset was applied and it will be constant (not changing right before reset asserted or clk edge) and that is why FF2 output will never be metastable
Ok
Correct answer !!!!
Glad to see your discussion !!
Metastability here is not due to data input but due to reset recovery and reset removal time. How is that not possible for FF2 ?
@@kamleshraiter658 if we look at the scenario before reset gets deasserted, input of FF1 is tied to logic 1 and output is 0, but in case of FF2, the input is 0 and the output is also 0. So there will be logic differential for FF1 once reset is deasserted in reset recovery time and output will oscillate i.e metastable.But not for FF2 as there is no logic differential. This is my understading. pls correct me if anything is ambiguous in my coclusion
Due to delay of 1 clock, 2nd flipflop is not in metastable.
Hello Sir, I can't find the video which just on the de-assertion of reset async reset ? would it be possible to get the link ?
Hello Ashmika,
I think, I created it long back. Even I could not find it because its title is different.
BTW, I will create a new one on your suggestion.
Sir, Please make a video on Glitch free clock muxing. Your videos are helping me a lot Thank you so much.
I have a question,
Im using clock gating in my design. My question is: the clock gating should affect the dual flop synchronizer or the synchronizer must have the free clock always?
if you are talking about dual flop synchronizer for data.. it depends upon your design architecture expectations. But w.r.t metastability, I dont think it will cause any issue.
if you are facing any issue, let me know we can discuss.
@@TechnicalBytes Hi, thank you for your reponse. I managed to fix it. The problem was not with the clock gating.
I have another question, if you could help me:
I'm using a handshake synchronizer, and I have control signals of it (Ack and Req). It is used in my FSM to control the data sent in one domain to another. However, the tool says that it is a convergence of signals (control signals synchronized combined in a logic). Do you know where I can find more informations if I should waive this problem or find another solution to avoid convergence of control signals of handshake synchronizer?
Very nice
Thanks
Since 2nd flip flop will sample after 1 cycle delay the input data would be stable but still if metastability of 1st FF makes output 0 instead of 1 or vice versa then even 2nd FF can go metastable . Please give your feedback regarding my answer
agree that 1st FF can give either 0 or 1 if it enters in metastable but that doesnt mean FF2 would enter in metastable as well.
nice
Thanks
If a data synchronizer is used as reset synchronizer by tieing it's data pin high..
Would it result in some kind of issue or it will work correctly?
Give a video presentation on how slow clock domain captures data from fast clock domain without losing data
Using fifo.
Restet assertion should be asynchronus and deassertion is synchronous so don,'t use data synchroniser
I did not find Part 2 for CDC . Can you please share the link ?
It is not created yet, but we will create it as per your request..
@@TechnicalBytes yes. please create part 2 and full series if indeed.
Assumption is MTBF is high for these flops , that's why 2nd flop is not going to metastable state
Didn't get what is clock domain crossing
Assume there is a flop F1 clocked by a clock signal, say clk1. We say this flop is in clk1 clock domain(or clock boundary, any other flops having clk1 as clock would be a part of the same clk1 clock domain). Another flop F2 clocked by a different flop, say clk2 is present in some other part of the design. If we need to send some input data signal to F2 from F1, this signal would cross(move) from clk1 domain to clk2 domain as the destination flop F2 is of clk2 domain. This incoming signal from F1 appears as asynchronous to the F2 flop as it is from a different clock domain and this may lead to metastability.
We can say that the input signal has crossed clock boundaries/domains (from clk1 to clk2) which is pretty much what a clock domain crossing (CDC) is.