Introduction to FPGA Part 9 - Phase-Locked Loop (PLL) and Glitches | Digi-Key Electronics

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  • เผยแพร่เมื่อ 5 ก.ย. 2024
  • A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.
    In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).
    Previously, we showed how to use block RAM to store data in an FPGA ( • Introduction to FPGA P... ). In this episode, we will see how to use a phase-locked loop (PLL) to increase the clock speed as well as discuss how glitches can occur.
    The solution to the challenge at the end of the episode can be found here: www.digikey.co...
    All code examples and solutions for this series can be found here: github.com/Sha...
    A phase-locked loop (PLL) is a digital circuit that produces a repeating pattern (e.g. sinewave, square wave) with a frequency and phase matched to the input reference signal. PLLs have many uses, including demodulation and clock multipliers.
    The iCE40 has a built-in PLL circuit that can be configured as a clock multiplier. The feedback mechanism contains a clock divider so that the voltage controlled oscillator (VCO) must output a clock that, when divided, matches the reference signal.
    In the video, we use the icepll tool to calculate the parameters necessary to produce a 120 MHz clock from the 12 MHz reference signal. We then output that faster clock to a pin and measure it with an oscilloscope.
    We introduce the concept of glitches, which are spurious transitions that may be incorrect data. For example, a simple adder circuit can introduce glitches due to gate delays. The carry bit takes some time to move through a simple ripple-carry adder/counter, and glitches can be seen on the output before the value is registered in flip-flops.
    We conclude with a challenge: can you think of another way to design a counter that reduces or eliminates glitches?
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ความคิดเห็น • 12

  • @johncutler5995
    @johncutler5995 2 ปีที่แล้ว +6

    Thanks Important info to know, but I'm starting to wonder if FPGA's are ultimately going to be too advanced for what's left of my 72 year old retired, hobbyist mind}

    • @saturdaysequalsyouth
      @saturdaysequalsyouth 2 ปีที่แล้ว +6

      Don't look at the latest Xilinx parts then :)

    • @emillyboschen6012
      @emillyboschen6012 9 หลายเดือนก่อน

      as a ee student i feel like i dont even used 2% of it potencial

  • @pratiksharma4238
    @pratiksharma4238 2 ปีที่แล้ว +3

    Thank you for such videos .. Digikey is doing great for the community. !

  • @233kosta
    @233kosta 10 หลายเดือนก่อน +2

    The awkward moment when my "good enough" 50MHz scope isn't quite good enough any more 😂

  • @TinLethax
    @TinLethax 2 ปีที่แล้ว +2

    Sadly my LP1K BGA 36 package doesn't come with PLL.

  • @bluedot7817
    @bluedot7817 2 ปีที่แล้ว +8

    My girlfriend told me she was leaving me for an FPGA, my mind was stuck in a phase-locked loop, I never saw the signals.

    • @franciscogerardohernandezr2319
      @franciscogerardohernandezr2319 หลายเดือนก่อน +1

      The worst part is when your DMs get second-order filtered, and she blames it on the phase noise.

    • @bluedot7817
      @bluedot7817 หลายเดือนก่อน

      @@franciscogerardohernandezr2319 And here I was blaming it on the low pass filter on the input, she did have a really high pitch voice. She told me she was into choking, but actually meant, wrapping wire around a ferrous core to disable DC current with an AC bias.

  • @candidmoe8741
    @candidmoe8741 2 ปีที่แล้ว +1

    How fast can you run the ICE40? Why 120 MHz and not 240 MHz?

  • @csqgb9801
    @csqgb9801 2 ปีที่แล้ว

    /search/换脸.html