9.7. Hierarchical design in VHDL

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One of the main philosophies of VHDL is hierarchical design. We have to be able to use smaller building blocks to build bigger designs. Multiple levels of hierarchy allow us to build ever larger and more complicated circuits. This is essential to managing complexity.

[@MoritzWallis]

Incredible videos, thank you so much. So well structured and easy to understand!

[@Dg2020]

thank you very much. helped a lot

[@keyvanshahin1740]

very helpful and fast slides. really appreciate. there are few notes I wanted to make. in a couple of chapters ago you noted that one should not use exp and div operands. that is not completely correct. most of the time people use them not for synthesized logic but for defining parameters and stuff before the synthesis so that the compiler can calculate the numbers and put them into code. Here also there was a small mistake. if you need a 16bit bus you should define it as 15 downto 0 not 16 downto 0. apart from these, the presentations are very helpful and compact. thanks again.

[@Tigerseen]

En verdad, muchas gracias, sin importar el idioma, explicaste muy bien 👍🏻👍🏻

[@anirudhas1940]

I believe the label is necessary for instantiating because I am literally unable to instantiate components without labels. It gives me errors.

[@nikolaykostishen6402]

Thanks! Very nice video.

[@shivakumarcheruku8838]

Hi I really appreciate your work, I need a video which helps me understanding flat vs hierarchical design in pnr

[@electrontube4284]

Thank you