How to use a Case-When statement in VHDL

Learn how to create a multiplexer in VHDL by using the Case-When statement. The Case-When statement is equivalent to a series of If-Then-Elsif-Else statements.
This is the blog post for this video:
vhdlwhiz.com/c...
The Case-When statement works similarly to the switch-statement in C or C++. It transfers control to one of several sub-branches, depending on the value of a signal or variable.
The syntax of the Case-When statement is:
case [expression] is
when [choice1] =＞
[code to perform when the expression equals choice1]
when [choice2] =＞
[code to perform when the expression equals choice2]
when others =＞
[code to perform when none of the choices were matched]
end case;
The [expression] is usually a signal or variable. If the value of the expression equals one of the choices, the code within that branch will be executed. A "break" statement is not needed like it is in a C/C++ switch-statements.
At the end of the Case-When statement, you may include a "when others" case. This branch will be chosen whenever the expression matches none of the branches.
Using the Case-When statement is the standard way of implementing a multiplexer, or MUX for short. It is also used for creating finite state machines, among other things.

[@AhmadAsmndr]

Thanks a lot, very helpful.

[@armina3470]

Thanks , it was a really helpful veido.

[@Tio_Sam00]

hello.
I'm doing homework and my professor asked us to do a state diagram in behavioral.. so I was following his steps during the homework. but when I try to synthesize it, it gives me this error ( case statement does not cover all choices. 'others' clause is needed) what that means?

[@VHDLwhiz]

It means that there are some possible values on the CASE signal/variable that are not covered by the WHEN branches. You can either add WHEN statements for the missing values or a single "WHEN OTHERS =>" that catches all values not covered by the other WHEN statements.

[@VHDLwhiz]

@@unstoppableguy7896 I'm not sure what you mean. Maybe you can get some help from my blog post about signed/unsigned types in VHDL: vhdlwhiz.com/signed-unsigned/
They use the two's complement to store positive and negative integers.

[@TheLeontheking]

Could we also have an array of signals, and use the selector value as an index to pick a value out of the array?

[@VHDLwhiz]

Yes, but it's easier to just use the selector to index the vector (or array) without using a CASE-WHEN statement:
signal sel : integer range 0 to 7;
signal s : std_logic_vector(7 downto 0);
begin
A_PROC : process
begin

report std_logic'image(s(sel));

wait;
end process;

[@simen9862]

Can the case statement also be defined concurrently like in the previous video?

[@VHDLwhiz]

No, but you can put the case-when statement in a function or procedure and call that concurrently.