9.18. Variables & signals in VHDL

www.electrontu...
Signals are fairly easy to understand, they are physical nodes in a circuit. Variables in VHDL can be a little challenging because they represent temporary storage locations more akin to a programming paradigm. But if you really want to be confused, check out how variables and signals behave in a process.

[@TareqKhan0]

Very good explanation.

[@mahmoudtantawi93]

Hi Dr. Karim, firstly thank you very much for this informative channel, and the videos are really helpful and greatly explained. Secondly I wonder what are the variables synthesized to in this case?

[@electrontube4284]

So variable synthesis is a very context-sensitive issue. It depends on how and where the variable is used. Most variables will synthesize into registers with values that are considered significant under certain conditions. Some variables will not synthesize into anything and will be implied by hardware for surrounding statements. In some conditions, variables may yield latches, but this requires some very bad coding. Most normal uses of variables will become registers.

[@andreabentivoglio764]

Thank you for this video, it was so much usefull!