Semantics aside. It doesn't matter, they are both metal contact points to the gate. As long as the pmos is connected to Vdd, bulk is connected to Vdd, and pmos is being used for strong 1's (pull-up).
Hello sir I regularly follow your video please suggest from where I learn online for analog layout from scratch to gds2 file suggest some video lecture or something for learn in analog layout design part
please upload a video of making.. a MIM Capacitor in layout. I am facing problem in making capacitor in cadence tool because i can't find Ploy2 in my cadence package. Please help
Sir, I've imported a GDSII layout of a spiral inductor from HFSS to Cadence virtuoso.I need to use this inductor in a circuit.How can I obtain its schematic from assura?Thanks in advance
cadence sucks... i was thinking this overpriced SW has at least some rubber-wires like KiCAD or protel98... it is really ridiculous, how can You layout more then a few parts like this?
why you are saying "drain of pmos is connected to Vdd".during this layout designing.It should be the source terminal.
Semantics aside. It doesn't matter, they are both metal contact points to the gate. As long as the pmos is connected to Vdd, bulk is connected to Vdd, and pmos is being used for strong 1's (pull-up).
Well done presentation. Nice including the parts on how to work through DRC errors.
It would be cool if you make a similar video for the CMOS XOR gate.
We don't really need to connect the drain and source of a stacked mosfet with separate metal, do we? we can just use shared uncontacted diffusion.
Ek number veere...sirra lata!!
really useful, thank you very much
Hello sir I regularly follow your video please suggest from where I learn online for analog layout from scratch to gds2 file suggest some video lecture or something for learn in analog layout design part
your way of explaining is really good, would you please do the layout for the same op-amp u designed before in 9 lectures
Here one doubt source terminal should connected to power right either pm os/nmos source terminal to vdd/gnd
extremely cumbersome to use this tool. it's really hilarious that a chip designing tool should be so bad
Thanks for the clear explanation
In analog circuit, polysilicon is avoided for gates connection. Kindly suggest what should be preffered then for connection.
thank you so much Mr hafeez
thank you for sharing valuable content
Very well explained
Thank you, Sir.
dear, do you offer any course for learning how to use this program ?
Oh my god handcraft layout drawing
Where can I download the primlib-library?
thaks a lot.....my friend
please upload a video of making.. a MIM Capacitor in layout. I am facing problem in making capacitor in cadence tool because i can't find Ploy2 in my cadence package. Please help
Thanks a lot!
during layout design with p shotcut am not getting guided path ...pls tell me solution
Thank you so much😭😭😭
sir How to align transistors properly ?
What software using for this
hello，i have a ic design ，can you help me to complete it？
plz explain abt GDI technology
Sir,
I've imported a GDSII layout of a spiral inductor from HFSS to Cadence virtuoso.I need to use this inductor in a circuit.How can I obtain its schematic from assura?Thanks in advance
thanks
Try to tell shortcut keys also
how install cadence virtuoso
cadence sucks... i was thinking this overpriced SW has at least some rubber-wires like KiCAD or protel98... it is really ridiculous, how can You layout more then a few parts like this?
Either this software is dead slow or you need a new computer ... 😀
You are wrong because in pmos source has at high potential
Thanks a lot !