How to Add PLL IP in your Design? | PLL in Qurtus | PLL Simulation in Modelsim

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[@muralikrishna612]

Instantiation of altera_pll failed design unit not found but RTL schematic is good but blank simulation error loading design

[@muralikrishna612]

I am getting simulation outputs for normal programs but ip core simulation i am facing errors

[@muralikrishna612]

I am getting error loading design in modelsim same procedure i followed can you please help i am using 20.1 altera , waiting for your reply

[@muralikrishna612]

What transcript you are showing in video

[@muralikrishna612]

I tried even three different versions no modelsim output