this is what I'm waiting for, thanks Shawn! update : I'm using iCE40 LP1K, please beware of BRAM read back timing. In dual port async ram, after wrote read_address to the BRAM module, data will arrive later after 2 read clock cycle.
@@ShawnHymel I found out that my BRAM as video buffer is sometime give s random 0 even all bits are 1. Then I searched on google, someone over 1bitsquare forum also talked about this behavior too.
@@TinLethax Thanks! I think I found the post on 1bitsquared. The OP talks about a 2 clock cycle delay for the UP5K models (but notes that the HX models are different). I looked at TN1250 p.4, and from what I can tell, rdata is invalid because re and rclke are low. I might be reading that chart incorrectly, though. I'll see if I can put together something to test the read delay on my iCEstick, as I'm really curious to know if there's such a delay on the HX model.
what is the difference between setting the flag to initialize the memory with the text file as double quote, instead of using 1? If that value is null, the init won't be triggered, but double quote isn't interpreted as null by Verilog?
Okay, I think I do not understand the mechanism of how the RAM is invoked. If I use [1:0] r_data and [1:0] w_data, 2-bit data, then I get "ICESTORM_RAM: 0/16 0%". And even if I use a full 8-bit data, I cannot invoke the RAM when calling from the main.v. The simulation works fine and the build works fine, but the hardware reads nothing (not random bits, but just zeros). If anyone has encountered and solved a similar problem, I'd greatly appreciate knowing.
I'm guessing you're asking about "programmable logic block" vs. "configurable logic block?" I think they're the same--I see CLB used most often in literature/content, but every now and then I see PLB. They seem to refer to the same thing from what I gathered.
Great series, please continue this.
this is what I'm waiting for, thanks Shawn!
update : I'm using iCE40 LP1K, please beware of BRAM read back timing. In dual port async ram, after wrote read_address to the BRAM module, data will arrive later after 2 read clock cycle.
Good to know, thank you! I'll see about pointing that out in a later episode
Where did you find that info? I can't seem to find it in the Datasheet nor in the BRAM Usage Guide.
@@ShawnHymel I found out that my BRAM as video buffer is sometime give s random 0 even all bits are 1. Then I searched on google, someone over 1bitsquare forum also talked about this behavior too.
@@ShawnHymel In TN1250 technical sheet page 4, the address and data is lack behind according to that timing diagram.
@@TinLethax Thanks! I think I found the post on 1bitsquared. The OP talks about a 2 clock cycle delay for the UP5K models (but notes that the HX models are different). I looked at TN1250 p.4, and from what I can tell, rdata is invalid because re and rclke are low. I might be reading that chart incorrectly, though. I'll see if I can put together something to test the read delay on my iCEstick, as I'm really curious to know if there's such a delay on the HX model.
This is the kind of marketing I prefer :)
😂
If LUTs can be used as ram, does that mean that LUTs can be configured on the fly? Can you dynamically reprogram ice40s while the device is running?
This is golden!
Great stuff as usual, thanks Shawn. A trivial question: what typeface are you using in NP++?
Ed. Got it: Consolas
Another awesome episode as always!
At 21:40, is an empty string "" considered null?
what is the difference between setting the flag to initialize the memory with the text file as double quote, instead of using 1? If that value is null, the init won't be triggered, but double quote isn't interpreted as null by Verilog?
Thank you!
eres muy listo :)
great video thx
i saw notepad++ in dark mode, hit like 😃 mousepad and leafpad is great in linux 😉
Okay, I think I do not understand the mechanism of how the RAM is invoked. If I use [1:0] r_data and [1:0] w_data, 2-bit data, then I get "ICESTORM_RAM: 0/16 0%". And even if I use a full 8-bit data, I cannot invoke the RAM when calling from the main.v. The simulation works fine and the build works fine, but the hardware reads nothing (not random bits, but just zeros).
If anyone has encountered and solved a similar problem, I'd greatly appreciate knowing.
If you only shown VHDL along Verilog, that would been great.
Are PLB and CLB the same?
I'm guessing you're asking about "programmable logic block" vs. "configurable logic block?" I think they're the same--I see CLB used most often in literature/content, but every now and then I see PLB. They seem to refer to the same thing from what I gathered.
@@ShawnHymel yes, I wanted to make sure seems like they refer to the same thing
If RAM is built in the FPGA, why did you spend IO pins? I thought IO pins are required to interact with the outside world