Introduction to FPGA Part 8 - Memory and Block RAM | Digi-Key Electronics

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.
In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).
Previously, we demonstrated how to create a Verilog testbench and simulate a design using Icarus Verilog ( • Introduction to FPGA P... ). In this episode, we look at using block RAM to store data.
The solution to the challenge at the end of the episode can be found here: www.digikey.co...
All code examples and solutions for this series can be found here: github.com/Sha...
Often you will need to store data in your digital design. This could be samples from a sensor, instructions for a CPU, or output from complex mathematical calculations. One obvious place to store data is in the D flip-flops in the logic cells. However, as each flip-flop can store only 1 bit, you would quickly waste most of your cells trying to store more than a few bytes.
One solution is to store data in the look-up tables (LUTs). This is known as “distributed RAM.” If you don’t need to store much data, your synthesis tool might allocate LUTs as distributed RAM. However, if you need to store more than a few bytes, you might be better off using block RAM.
A block RAM is a contiguous piece of memory that exists alongside the reprogrammable fabric. In most cases, block RAM is reconfigurable to a number of widths and depths. We can use system functions (denoted with a ‘$’) to allocate block RAM, but these commands are often unique to a particular synthesis tool.
Instead, we will write pure Verilog code that describes the behavior of the RAM. The synthesis tool will infer that we want to use block RAM and allocate it for us.
Additionally, we can write a text file with initial RAM values if we wish to have the synthesis tool load those values into RAM during the FPGA configuration process.
Your challenge is to create a simple 2-bit sequencer that records and plays up to 8 steps. You should use two buttons to enter a pattern and another button to record that pattern to memory. Meanwhile, the FPGA should be looping through the memory elements (e.g. 8 memory elements) and displaying the stored patterns on 2 of the LEDs.
Product Links:
www.digikey.co...
Related Videos:
• Cyclone® III FPGA
• Power Management: Powe...
• FPGA's: Low-Cost, High...
Related Project Links:
www.digikey.co...
Related Articles:
www.digikey.co...
www.digikey.co...
Learn more:
Maker.io - www.digikey.co...
Digi-Key’s Blog - TheCircuit www.digikey.co...
Connect with Digi-Key on Facebook / digikey.electronics
And follow us on Twitter / digikey

[@rishab9761]

Great series, please continue this.

[@yorickmeulenbelt4all]

This is the kind of marketing I prefer :)

[@anonymousinfinido2540]

😂

[@TinLethax]

this is what I'm waiting for, thanks Shawn!
update : I'm using iCE40 LP1K, please beware of BRAM read back timing. In dual port async ram, after wrote read_address to the BRAM module, data will arrive later after 2 read clock cycle.

[@ShawnHymel]

Good to know, thank you! I'll see about pointing that out in a later episode

[@ShawnHymel]

Where did you find that info? I can't seem to find it in the Datasheet nor in the BRAM Usage Guide.

[@TinLethax]

@@ShawnHymel I found out that my BRAM as video buffer is sometime give s random 0 even all bits are 1. Then I searched on google, someone over 1bitsquare forum also talked about this behavior too.

[@TinLethax]

@@ShawnHymel In TN1250 technical sheet page 4, the address and data is lack behind according to that timing diagram.

[@ShawnHymel]

@@TinLethax Thanks! I think I found the post on 1bitsquared. The OP talks about a 2 clock cycle delay for the UP5K models (but notes that the HX models are different). I looked at TN1250 p.4, and from what I can tell, rdata is invalid because re and rclke are low. I might be reading that chart incorrectly, though. I'll see if I can put together something to test the read delay on my iCEstick, as I'm really curious to know if there's such a delay on the HX model.

[@CrimsonTide001]

If LUTs can be used as ram, does that mean that LUTs can be configured on the fly? Can you dynamically reprogram ice40s while the device is running?

[@dorukbu3133]

This is golden!

[@Dinkleberg96]

Another awesome episode as always!

[@seankayll9017]

Great stuff as usual, thanks Shawn. A trivial question: what typeface are you using in NP++?
Ed. Got it: Consolas

[@jmssun]

Thank you!

[@erikvanzijst]

At 21:40, is an empty string "" considered null?

[@fcf8269]

what is the difference between setting the flag to initialize the memory with the text file as double quote, instead of using 1? If that value is null, the init won't be triggered, but double quote isn't interpreted as null by Verilog?

[@petercheung63]

great video thx

[@AndreaHerreriasLeon]

eres muy listo :)

[@tinglin6121]

Okay, I think I do not understand the mechanism of how the RAM is invoked. If I use [1:0] r_data and [1:0] w_data, 2-bit data, then I get "ICESTORM_RAM: 0/16 0%". And even if I use a full 8-bit data, I cannot invoke the RAM when calling from the main.v. The simulation works fine and the build works fine, but the hardware reads nothing (not random bits, but just zeros).
If anyone has encountered and solved a similar problem, I'd greatly appreciate knowing.

[@EEStopXplore]

If you only shown VHDL along Verilog, that would been great.

[@midoucis9274]

Are PLB and CLB the same?

[@ShawnHymel]

I'm guessing you're asking about "programmable logic block" vs. "configurable logic block?" I think they're the same--I see CLB used most often in literature/content, but every now and then I see PLB. They seem to refer to the same thing from what I gathered.

[@midoucis9274]

@@ShawnHymel yes, I wanted to make sure seems like they refer to the same thing

[@lukaspfitscher8737]

i saw notepad++ in dark mode, hit like 😃 mousepad and leafpad is great in linux 😉

[@falrus]

If RAM is built in the FPGA, why did you spend IO pins? I thought IO pins are required to interact with the outside world