My compliments - I'm really enjoying this series. I haven't bought the hardware yet but I'm planning to quite soon. I think the pace and level of detail in this series is perfectly pitched - there is good initial information in here, and if the student wants to learn more, well... there's a whole internet to search for material. My compliments on a genuinely useful, concise series of videos.
Thank you...I'm really glad you're enjoying the series! I found that much of the information for using Verilog and FPGA tools is rather scattered (save for a couple of books and videos). My hope is that the series can give people the basic building blocks for using Verilog to start making their own FPGA projects (or at least understanding other people's projects).
Although I already have a DE10-Standard board, I placed an order for an Ice Stick because of your tutorials. Now all I'm missing is a breadboard with a bunch of buttons and LEDs, because this one doesn't come with much, but no complaints. Might get one of those cheap-generic "Arduino compatible" cases you generally see on Aliexpress \ Amazon and call it a day. Would be nice to be able to show my friends what an FPGA is, beacuse I'm not taking my DE10 out of the dorms, lol.
[COUNT_WIDTH:0] is actually COUNT_WIDTH+1 bits wide, as 0 was included. This isn't terribly important in this case, as it just needs to be wide enough to hold MAX_COUNT and narrow enough to fit and satisfy timing; if you're lucky, the synthesizer might even tell that the top bit is constant and remove it. Personally I prefer the #() syntax for setting parameters over defparam, e.g.: clock_divider #(.COUNT_WIDTH(32), .MAX_COUNT(1500000-1)) div_1(.clk(clk), .rst(rst), .out(led[0])); This avoids repeating the instance name and makes it easy to define multiple instances with the same parameters. Note that you don't have to match styles between the module definition and instantiation; they're parameters either way.
Thank ou for making this series. It is very helpful to get your concise take on using FPGA's. My question is are you going to do an episode describing how to use ICESTUDIO and/or GTK Wave? I know you seem to be a windows guy, but many of us are linux users, and it would be very helpful to have some episodes addressing more free tools that we could use.
I try to pick tools that work across all the major operating systems, so everything I show *should* work on Linux and macOS as well as Windows (some of the installation commands might be a little different). That being said, I believe iverilog and GTKWave is the next episode :) I like what IceStudio is doing, but I don't think I'll have time to fit it into the series. I decided to cover modifying a RISC-V softcore processor in the last two episodes instead of IceStudio (or some other topics). I tinkered with IceStudio, and it's pretty easy to set up and use. If you can manage your way with command-line tools, I think IceStudio would be even easier.
Excellent series Shawn. Top drawer & nice and snappy. No waiting for slow typing and droning-on! Does mean I have to occasionally rewind 🤠. Had an .apio issue with sample code for a couple of dev boards where the verilog in other module files was included in the top.v file using the ‘include metastatement. I’m assuming needed for some tool chains but apio is doing a sweep of all files in the folder to round up other modules instantiated elsewhere. So with the file include statement(s) you get an error from apio that the module is already declared. Might help someone…. But apio is great & enjoying Verilog instead of my usual VHDL.
In the world of programming languages one can take a module written in one language (e.g. GUI written in C++), a module written in another language (e.g. a numerical library written in Fortran) and under some circumstances link them into one executable. Is it possible in the world of HDLs? If yes, could you prepare a simple tutorial? I think it is a valid question as there are many open source cores written in different HDLs and one may want to "glue" e.g. a processor described in VHDL with a peripheral described in Verilog. Greetings from Poland.
From what I understand, some synthesis and simulator tools do allow you to mix languages among your modules, but it depends on which toolset you're using. I have not personally seen it done, but I'll keep in mind that there's interest in a tutorial for that!
My compliments - I'm really enjoying this series. I haven't bought the hardware yet but I'm planning to quite soon. I think the pace and level of detail in this series is perfectly pitched - there is good initial information in here, and if the student wants to learn more, well... there's a whole internet to search for material. My compliments on a genuinely useful, concise series of videos.
Thank you...I'm really glad you're enjoying the series! I found that much of the information for using Verilog and FPGA tools is rather scattered (save for a couple of books and videos). My hope is that the series can give people the basic building blocks for using Verilog to start making their own FPGA projects (or at least understanding other people's projects).
"I haven't bought the hardware yet but I'm planning to quite soon" Good luck with that, it is out of stock since part1 :)
@Shawn Hymel HUGE thanks for the dark themed video, much easier on the old eyes ;-)
Although I already have a DE10-Standard board, I placed an order for an Ice Stick because of your tutorials.
Now all I'm missing is a breadboard with a bunch of buttons and LEDs, because this one doesn't come with much, but no complaints. Might get one of those cheap-generic "Arduino compatible" cases you generally see on Aliexpress \ Amazon and call it a day.
Would be nice to be able to show my friends what an FPGA is, beacuse I'm not taking my DE10 out of the dorms, lol.
[COUNT_WIDTH:0] is actually COUNT_WIDTH+1 bits wide, as 0 was included. This isn't terribly important in this case, as it just needs to be wide enough to hold MAX_COUNT and narrow enough to fit and satisfy timing; if you're lucky, the synthesizer might even tell that the top bit is constant and remove it.
Personally I prefer the #() syntax for setting parameters over defparam, e.g.:
clock_divider #(.COUNT_WIDTH(32), .MAX_COUNT(1500000-1)) div_1(.clk(clk), .rst(rst), .out(led[0]));
This avoids repeating the instance name and makes it easy to define multiple instances with the same parameters. Note that you don't have to match styles between the module definition and instantiation; they're parameters either way.
Good catch, thanks! I found the MAX_COUNT one, but I forgot to update the bit width parameter.
Muito Obrigado por democratizar esse conhecimento ❤
Thank ou for making this series. It is very helpful to get your concise take on using FPGA's. My question is are you going to do an episode describing how to use ICESTUDIO and/or GTK Wave?
I know you seem to be a windows guy, but many of us are linux users, and it would be very helpful to have some episodes addressing more free tools that we could use.
I try to pick tools that work across all the major operating systems, so everything I show *should* work on Linux and macOS as well as Windows (some of the installation commands might be a little different). That being said, I believe iverilog and GTKWave is the next episode :)
I like what IceStudio is doing, but I don't think I'll have time to fit it into the series. I decided to cover modifying a RISC-V softcore processor in the last two episodes instead of IceStudio (or some other topics). I tinkered with IceStudio, and it's pretty easy to set up and use. If you can manage your way with command-line tools, I think IceStudio would be even easier.
Excellent series Shawn. Top drawer & nice and snappy. No waiting for slow typing and droning-on! Does mean I have to occasionally rewind 🤠.
Had an .apio issue with sample code for a couple of dev boards where the verilog in other module files was included in the top.v file using the ‘include metastatement. I’m assuming needed for some tool chains but apio is doing a sweep of all files in the folder to round up other modules instantiated elsewhere. So with the file include statement(s) you get an error from apio that the module is already declared.
Might help someone…. But apio is great & enjoying Verilog instead of my usual VHDL.
🔥🔥🔥🔥🔥
In the world of programming languages one can take a module written in one language (e.g. GUI written in C++), a module written in another language (e.g. a numerical library written in Fortran) and under some circumstances link them into one executable. Is it possible in the world of HDLs? If yes, could you prepare a simple tutorial? I think it is a valid question as there are many open source cores written in different HDLs and one may want to "glue" e.g. a processor described in VHDL with a peripheral described in Verilog. Greetings from Poland.
From what I understand, some synthesis and simulator tools do allow you to mix languages among your modules, but it depends on which toolset you're using. I have not personally seen it done, but I'll keep in mind that there's interest in a tutorial for that!
Get a Zynq and combine your RTOS/embedded linux series with FPGA.