Introduction to FPGA Part 7 - Verilog Testbenches and Simulation | Digi-Key Electronics

A field-programmable gate array (FPGA) is an integrated circuit (IC) that lets you implement custom digital circuits. You can use an FPGA to create optimized digital logic for things like digital signal processing (DSP), machine learning, and cryptocurrency mining. Because of the FPGA’s flexibility, you can often implement entire processors using its digital logic. You can find FPGAs in consumer electronics, satellites, and in servers used to perform specialized calculations.
In this series, we will see how an FPGA works and demonstrate how to create custom digital logic using the Verilog hardware description language (HDL).
Previously, we showed how to create modules in Verilog and use parameters to change the functionality of instantiated modules ( • Introduction to FPGA P... ). We’ll build on those concepts in this video, where we demonstrate how to create a testbench in Verilog, simulate the design with Icarus Verilog (iverilog), and view the output waveform with GTKWave.
The solution to the challenge at the end of the episode can be found here: www.digikey.com/en/maker/proj...
All code examples and solutions for this series can be found here: github.com/ShawnHymel/introdu...
Uploading your design to a real FPGA can sometimes take a while (especially for larger designs and denser FPGAs). Additionally, to check the timing and operation for fast-changing signals (think RAM bus or USB signals), you would need other specialized test equipment, such as a logic analyzer. Connecting all of the FPGA pins to a logic analyzer can also be a time-consuming processor.
To save us time, we can write Verilog code that tests our design (known as a “testbench”). We use a special simulation program (Icarus Verilog, in our case) to run the testbench code. The testbench code should instantiate the module(s) under test (often called a “unit under test” or “uut”) and toggle the necessary input lines.
The simulation will run our testbench, and it will log all how and when the various signals/wires change in the design. It will store this log in a “value change dumpfile” (.vcd). We can use a waveform viewer, such as GTKWave, to visualize these changes. The waveforms should look similar to what you might find on a logic analyzer.
Your challenge is to create a Verilog testbench for your button debouncing code from episode 5. You are welcome to use my solution to that challenge as a starting point (github.com/ShawnHymel/introdu.... Note that you might need to make some changes to the original code to allow for passing parameters to the design.
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[@theomacphail7687]

This is an amazingly helpful series! Thank you for making the internet a more knowledgeable place.

[@Ic37r011]

Shawn you got me started with your class on Udemy. Then I stumbled upon this Digi-Key. I like your clear and clean instructions and explanations. Glad I found it.

[@ShawnHymel]

Welcome, and thank you--I'm really glad you like my teaching style!

[@seankayll9017]

Great info as usual. Thanks Shawn!

[@vaniaeli4392]

Muito Obrigado por democratizar esse conhecimento ❤

[@radekhladik7895]

And also a quick note:
the # delay command needs to be terminated with semicolon ; or have a command with semicolon after it.
So for example in the code:
#10
rst_btn = 0;
the #10 line is using the semicolon after the rst_btn=0

[@ShawnHymel]

Ah! Good to know, thank you.

[@CrimsonTide001]

At some point can you cover clock networks/PLLs? Nearly every FPGA has a huge section of their datasheet discussing clock networks, clock pins, buffers, and a half dozen other things I'm never quite sure how they act together, if I need them, when I would need them, and how I use/interact with them in verilog.

[@ShawnHymel]

I plan to show how to use the PLL in the IceStick in a future episode, but I don't plan to get into full clock networks. I'll also briefly talk about glitches and metastability.

[@johningram7399]

I looked at the solution for the challenge verses what was shown in the video for creating test benches and you would be hard pressed to come the final solution with out additional help and resources. The video covers a binary counter and challenge a FSM, I am not sure for a beginner how would solve it on your own.

[@sami-pl]

Any pointers for automation of tests ?

[@ze2411]

How to display the value of parameters and localparamereters in the verilog code in gtkwave?

[@aleXelaMec]

Am i understand right, the simulation goes Only on the PC and not on the chip itself. Then how we can be sure that the simulator and the real chip will work the same?!
Thanks for vids.

[@Ali-wf9ef]

To the ones not very familiar with HDLs, I suggest using VHDL instead of Verilog. Much more features, very good structure and easier in simulation