Long text about estimating output impedance if you don't have a good simulator at hand, its been very helpful at my work so i'd like to share: It's hard to specify an exact output impedance of drivers since the resistance of the output switches (mosfets in our case) will differ depending on the drive voltage and such. Meaning that lower VCC levels will lead to higher output impedance. If i recall correctly this is not a 100% accurate, but will give you a decent estimate of a drivers output impedance. And as a general rule of thumb for LVC drivers specifically 20-33ohms are usually good. If you change to a different family of drivers you will need to estimate their output impedance too, here is an example that has work well for me with numbers available in all datasheets (also for MCUs!). Using numbers from the "Electrical Characteristics" table in the datasheet, find the output voltage section (Voh, Vol). Under test conditions you will find the output current they used to get the numbers, for the parts used in the video (SN74LVC1G17) you will se that when driving low, when powered from 4.5V, with an output current of 32mA, the pin will read as 0.55V. If you calculate resistance from voltage and current (R=V/I) you get this calculation: 0.55/0.032 = close to 17 ohm. For high drive you will need to calculate the voltage drop inside the driver by taking VCC-Voh (4.5-3.8) = 0.7, which yields 0.7/0.032 = close to 22 ohm. You can do this for the rest of the VCCs listed in the datasheet. As mentioned before, its hard to give a specific number because the impedance comes from a complicated part such as a mosfet or bjt, but you get ball park values at least. 4.5V VCC: drive high: 22 ohm drive low: 17 ohm Which makes a 33 ohm resistor good for a 50 ohm track because: 22+33 = 55 ohm 17+33 = 50 ohm Both which are exactly or close to 50 ohm 2.3V VCC: drive high: 50 ohm drive low: 38 ohm 50+33 = 83 ohm 38+33 = 71 ohm Not 50 ohm, in this case it may be better to not use any external resistance since the average output impedance of going both high and low should be 44 ohms. Or add a 6 ohm resistor to minimize both errors as much as possible. Then again, the numbers we get from doing this calculation is not perfect, and if you do the calculations with numbers where VCC is the same but the output current differs you will also get different impedances (using Vol for the part used in the video, with VCC = 3V, 16mA output current is estimated to be around 25ohm, but with an output current of 24mA you get around 23ohms). It's still worth doing the calculations though, since we have used drivers with around 75 ohm impedance at work before, meaning that any added resistance for a 50 ohm track only make things worse, so long as the resistance is not high enough to slow down the rise time enough that your trace looks relatively short verses your wave length again. And STM32 micro controllers generally have 50 ohm output impedance when using "high drive strength" settings. So no added resistance there too if you are using 50 ohm tracks. You could also try using 20ohm tracks with the SN74LVC drivers, and you should have less issues too.
Nice video and also tips about the impedance calculations. I used this idea recently. It’s worth to keep in mind the Vil and Vih of the receiver together with the Vcc and series resistor at the output buffer. The voltage caused by the potential division might be reduced and may not drive properly. This is in the case you have a termination resistor too.
And you should consider the 32mA on the datasheet even if the output is connected to a CMOS high impedance input? This is due to the max current on the transition? Or this current is related with the load. I have a project here with 22R everywhere, even on the output pins of the CPU. I will take a look is the datasheet days something about impedance on the outputs. Thank you.
Excellent! I love these videos. They are very informative and educational. Also, these kinda need to be long, you can't give such a thorough demonstration and explanation in 5 or 10 minutes. That's why your videos are excellent, because you take the time to actually care about what you are doing.
I think 2 more improvements can be tested. 1. Tie victim buffer input terminal to ground. 2. Place decoupling caps to all buffers near the supply pins. Thank you so much Robert. By the help of these videos, even we can not simulate our boards, we can visualize the signals while routing. You are our hero thanks again :)
1) you mean like with a pull down resistor? When the reflection gets back, the netto resistance will be like a parallel resistor couple, while you need to be close to the line impedance. With a big pull down it appears like a open. In my opinion contributes to ringing. 2) what would the function be of the decoupling cap? Of course chosen correctly to prevent to act like an inductor, it would slow the rise/fall of the signal. And would act like a short for high freq signals. So act like a short and contribute to ringing.
It is just what makes engineering and the physics behind it interesting and worthwhile - the “Oh, wow, now I get it” or “That is great, even better than I thought” that happens for a blink of an eye. I actually learn most valuable things from videos which incorporate these moments - because nothing is better than learning through (contagious) enthusiasm.
The value of this video to me in its density of intuitive understanding of several complex ideas (high frequency signaling, the consequences of component rise and fall times, impedance matching, crosstalk), is so high that I think this is one of the best videos on electronics I have ever seen.
Thank you for another brilliant video! I was just routing some i2s lines that go from an SPDIF receiver to a DSP when watching this. I was thinking about skipping the series resistor because I read somewhere that it didn't really matter that much. I'm very glad I watched this video, and my circuit now has length-matched tracks and series resistors.
Robert Feneral.... I want to thank you in a really big fashion... the input you provide is a huge help.... more engineers and TEACHERs like you that share their knowledge are necessary.... the best awards are granted to your level of commitment.... my best regards to you and to your company
Back in 2016 I was set to design a PCB with 16 pressure sensors hooked up to a uC over a single SPI bus on a distance of over 20cm. Clock 8/9MHz can't remember. Whereas everybody was thinking of a noob project, I mean, 8/9MHz, how low is that 😅, I was already suspicious by intuition, not so much because of the frequency but especially because of the high fanout load. I got myself LT SPICE, took the rule of thumb numbers as 10nH per cm for the traces, don't remember for capacitance, and, for each input, the input impedance stated by the datasheet (roughly 1Meg and 10pF). Started the simulation.... we sat speechless in front of the transient analysis... It was clear it would never have worked without adequate considerations. We added those series resistors here and there, tried various values and managed to eventually get a good signal integrity. 1st PCB release worked perfectly but only thanks to that simulation. That's when I understood how critical things can be at even low frequency and remembered me, at the end, it's not only the frequency, it's the relationship of frequency and impedance ^^
Thanks for sharing your experience. As a fellow electronics engineer, I can confirm that if you want to do something right, it's totally worth spending the time and putting in that little extra effort at the early stages of prototype development. I've seen PWM signal distortion happening even at 100kHz! Signal rise/fall time, path length and grounding are key parameters.
@@elektrofreak-andg Absolutely. It is an often overseen one, the rise/fall time. And with modern digital logic, we also fell into that one in a project in 2011. Changed an old buffer (obsolete) for a "replace with" part. Didn't work anmore. What the heck... we got desperate... until 💡: what are the rise/fall times of the new one... Oohhhh, there it is ^^
Hey Robert, Thanks for the video. It covers some of the basic SI principles and I'm glad you made this video because it can make my life as an SI/PI Engineer easier if someone like you is approaching something like this. An important thing to mention that you did not is that the IBIS models allow you to also check how the signal will look like directly on the die of the component. Proper IBIS models have package parasitics, and pin parasitics (R L C) added in their models. This means that a signal might look good at the pin (where someone can physically measure with an oscilloscope) but at the die it can fail due to added inductance of the wirebonds and capacitance. Hope this adds some valuabe information :) P.S: I'm glad that someone finally explained why it's not all about frequency but about rise/fall times. I've seen 1MHz signals fail SI because they had 200ps rise/fall times and no terminations.
As Darko Obretan pointed out, the 2GHz wavelength in FR4 would be probably more like 80mm (3150mil) (?). I should use a different calculator, for example like this: www.pasternack.jp/t-calculator-phase-length.aspx
Great video once again, thanks! Regarding measuring this on your scope, it's not just about the scope bandwidth but you will need a good probe as well. My cheap 10x probes have about 15pF capacitance, at 100MHz. This translates in putting a load impedance of about 100 ohm (1/(2*pi*f*C)) on the line you are measuring. That should give you quite some effect already as you've now added a partial termination to the circuit!
Great Video !!!! In my opinion U need to make it with respect to capacity and inductance ... it is like Smith Chart by design of 50 Ohm line on the PCB, if Urs output is 18 Ohm U need to put some termination and to get 50 on line if the line out is 200 U need use Caps in pico to absorb this "energy" from going back but U changing this 200 to 50 in line of inductance and capacity. on the end of line. In RF the One way is to make wider tracks to get more of pF just look for strip-line filters they 100% Use this technique.
That's very interesting study. I have a couple of questions: 1) is the software validated, I mean which is the confidence level in the results. Software clearly show interesting "trends" but what about real measure of peak values? 2) I will be very interested in seeing a real PCB and repeat the same experiment you have proposed in this video. Can you do or can any on your follower do the test and share the plots?
In many situations, where the rising/falling time is too faster than needed in the application, slow it down by modifying the GPIO settings (configure output strength) or simply adding a small capacitor. The critical length is significantly increased.
For the output impedance of the buffer, since you have the IBIS model, put a 50 ohms termination at the ouput and measure the voltage at the resistor 50 ohms relative to ground on simulation. then uses a voltage divider equation and solve for the value of Rseries in the buffer. You can figure out the actual real part of the impedance. Then Zs of the buffer plus series termination should equal the transmission line impedance.
The reason for using 33 Ohm - you are trying to match the buffers output impedance to 50 Ohm, lets say you have a SN74LVC1G126, when the outputs is low, its parameters are max 0.55V @ 32mA = 17.2 Ohm output impedance. With 33 Ohm you get 50 Ohm :) This also means that this resistor value should be output specific, in order to get 50 Ohm output impedance. The resistor also needs to be placed as closed to buffers output as possible, so it appears as a single impedance.
But if the your sn74 output it's connected to CMOS input or microcontroller. The current will be 0mA due to high impedance of this inputs right? On this case you should use 50ohms? I did not understood why you consider the 32mA. It's due to the max current during the transition from 5V to 0V? Or due to the load current
Such a meaningful video for me. I almost forgot that it's the rise/fall time matters rather than the frequency of the signal. That's why I was surprised by the simulation results and think: why 10Mhz signal will cause reflection?? Thanks Robert :)
By matching the output impedance (driver + 33ohm), the reflection off the high impedance buffer at the end reflects back to the driver and the reflection is fully damped by the matched impedance of the driver to the 50 ohm transmission line.
Thank you for sharing. Impedance matching is the key. It's unrealistic to expect such a short trace for most of ICs input and output on a complicated PCB, so short in/out PCB trace solution isn't a practice solution to resolve the noise issue.
Hands down this is your best video so far!!!! It shows how much we've all learned thanks to your previous videos. Really, really good one. Thank you, Robert. There's one thing still bothering me, and it's your explanation as of why the dumping resistors improved the signal quality: was it really because you've got closer to the "magic" 50 ohms value, or was it because you've lowered the rising/falling time of the signal by creating an RC filter?
Great job Robert, thank you for such an educational tutorial. on 31:52 You mentioned that you believe one side matching is enough to remove ringing. I know that a proper Termination resistor removes the ringing. But how to be sure if there is a termination resistor in high impedance buffer input? It would be great if you make a video about NanoVNA usage for impedance checking or a video about how to design shields for noise immunity
Thank you Mustafa. PS: there is normally no termination on input of a standard buffer. Also, if there would be you need to be very careful as you may be creating voltage divider (depends on what kind of termination is used on output and what kind of termination is used on input).
Even if the the clock speed is only 10Mhz, the rise/fall times are 2 - 3 ns, meaning you need to apply RF thinking in the layout, i.e. trace impedance, via impedance, source and termination impedance, ground planes, via stiching etc. As 4-layer boards are so low cost, using 2-layers for digital, would make reasonable tracks a bit wide on 1.6mm boards.
Someone may have already asked this, but could you get a close impedance match on the high-impedance input-end of the tracks by shunting ~50 ohms to ground at the inputs? Wouldn't that eliminate or greatly reduce any reflections? I ask because two of the three approaches here--the stackup thickness which would require more than two layers, and matching the length of branching traces--are not always practical (or at least not always desired for economy or size contraints). The work I do is limited to inexpensive two-layer, .0.063, FR-4 boards.
Fyi, if the input capacitance of the buffers gets large (say driving 8 or more buffers in parallel) you can improve the rise time of the signal at the buffer by placing the series termination resistor right in front of the buffer. In this case the track is acting like a critically damped RLC circuit instead of a transmission line.
You should also separate the two outputs from the drivers by some space to reduce the crosstalk. The crosstalk is proportional to the length the two traces run in parallel. The longer the parallel tracks, the higher the crosstalk.
Hi Robert. I want to ask some thing. At time 36:00 you calculating frequency from falling edge and it's time 0.5ns (1/x). This calculation is, I think, wrong. Or does it? Here is why: In one period, there is always 4 edges, 2 rising and 2 falling. Therefore calculation has to be 1/(0.5 x 4) to get right frequency 500Mhz and not 2Ghz. I verified this through on my system where I measured with my 1GSa/s oscilloscope, 2.6ns falling edge. I saw also ringing where I marked full period of sinewave and oscilloscope gave me 110MHz frequency which is close enough and this also supported my thinking. What do you think? Btw I enjoy your work. Keep going! Correction: Oh. I think now we are both wrong :) In one period is only 2 full edges (or 4 half edges). Therefore 1/(0.5 x 2) will be right. I fount also mistake on my oscilloscope where it calculates fall time from whole first voltage peak which is also wrong. Be this for everyone as warning to not depend on oscilloscope time readings of fall, or rise edges because this calculation can be wrong as much as bigger is first spike.
Very nice. Interesting subject and superb presentation/demonstration... Presenting results with longer rise times and fall times is of interest. Thank you.
Dear sir your all videos are awesome really help full with correct information, I just only says to you pls make your video part wise , pls don't make it longer thank 20 to 30 minutes. It will give you the maximum watch time. Maximum the revenue.
21:39 Huh, I don't understand why we don't see any reflections from one BUF-INPUT onto another (and secondary reflections from forking point for that matter)
When reflections are high on both ends, the signal can bounce around and you can have standing waves, and the length of the track will decides the modes allowed, when the length is short enough no mode will be allowed. The "nominal" frequency number really doesn't matter because the signals are more like square waves and when you do a fourier transform on them a perfect square wave would have all frequencies (from 0 to inf), for real signals the rise and fall time will decide the fourier transform result and thus the frequency distribution. The only time when the nominal frequency is the real frequency is when the signal is a sinusoidal signal where a fourier transform will result in one point in the frequency domain, which could be the case in some RF situations. Also I would keep the tracks further apart so that the H and E fields generated by one signal would have less effects the other track.
I saw some circuits where the designer use a zero ohm resistor in the pi antenna circuit. As I understand those zero ohm resistors are zero ohm at 0Hz but at 2GHz the narrow path inside the resistor has a high impedance for a microwave.
A zero Ohm resistor is used if the antenna does not need tuning. The pi network is often included just as a precaution. You could also use a relatively large capacitor instead of the resistor.
Very impressing education showing us these hidden potholes in circuit design. for me the termination not only reduce the bounce back affect but it should also decrease the velocity of the output so that the first re bounce is not that strong as well i think. my first guess to your solution was to use resistors to reduce the ringing and also use ground plane to reduce the interference but I overlooked the length matching at first but that is rather obvious when you said it. I recall this length matching on boards was initially made to impedance match the traces but that they also serve the role to match the wavelength was less known to me so I actually learned something new here too. I have not built anything yet that works with this frequency but I do make oscillators that runs up to about 100khz or so and this generally won´t give you much problems that easy but I tend to use terminal resistors and also pulldown resistors to ground to reduce the noise between stages sometimes. but what I build is mostly control circuitry for amplifiers and powersupplies, timers and feedback or protection and mode indication stuff which I use for the tube amplifiers I also make for myself.
Please do the simulation with increased track width. You going to get pretty interesting result, caused by parasitic inductance of the tracks. So, it's basically a rule of thumb to keep whole stackup and tracks 50 Om matched.
Hi Robert, interesting video indeed. While 2 out of three solutions were no surprise to me (impedance matching track and buffer output), the stub length matching was. Maybe you could make a follow-up video going deeper into the signal split and stub length and explain better what happens there.
Funny things happen, due to different trace delays and splitting power at the 3 trace junction. Evey time a signal comes to the junction it splits into two signals 50% the power (same voltage, half the current). Case with matched series resistor: a) A=>J=>B1 (delay T0+T1) b) A=>J=>B2 (delay T0+T2) At B1 & B2 receivers the signals reflect going back (100% power, 0 Phase shift due to high impedence end) aa) B1=>J=>A (delay T1+T0) ab) B1=>J=>B2 (delay T1+T2) ba) B2=>J=>A (delay T2+T0) bb) B2=>J=>B1 (delay T2+T1) Signals at driver have nearly no reflection (~0% power), but signals ab & bb reflect again at the receivers. So signals bounce between B1 and B2 going lower and lower in power as the signals split and the ones going back to the driver are dissipated. When the lengths are not balanced there are many echoes out of sync => high frequency oscillations seen in simulation. In case of balanced arms the echoes are in sync, so lower frequency oscillations occur. P.S. Fun fact: In flyby layout (no junction, just route thrugh/by on B1: A->B1->B2) there is a delay between B1 and B2 received signals, but also there is only one signal reflected and that one is finally dissipated in the driver series resistor: A=>B1=>B2=>B1=>A
@@icestormfr nice explanation and it makes total sense. In a nutshell, it's about the reflected signals traveling between the stubs. but even if they are matched in length, the split of the reflected signals does happen. Maybe, additionally, in case of matched stub length, the reflections cancel (at least down the 2 stubs).
@@marcgoovaerts2614 yes and no 😅 They could cancel if one arm was open ended (high impedance) and the other shorted (low impedance) and the lengths balanced. One reflected wave would have inverted sign (shorted end: incident wave and inverted wave add to zero volt). When they meet at the junction the waves going back to the driver would cancel each other, but each wave going to the other receiver would still be there.
Oops, I was probably a bit too fast about my conclusion what happens at the junction when the two reflected waves from balanced arms arrive. Have to think about again, but could be that the waves combine without the extra reflection into the other arms 😅 (T junction Power Divide Theory)
Nice explanations of SI basics, the use of sigrity tools in your video is really cool as it show how things works. Also yo show how simulation evolve with change this is really a good idea to understand the feeling of physics behind. Thanks for your video, thanks for your clearly understandable english even for a french guy :)
The wavelength that matters is the wavelength in the medium (FR4), not the wavelength in vacuum (which is what you calculated). You need to shorten it by a factor of 1/sqrt(Er)
Thanks a lot for this video! It is indeed very useful! You are a very good teacher! A question for you, would it be even better to add 50R resistor to your buffers inputs? thanks again for this!
So shortly: Lenght matching eliminates ringing. Changing stack-up moves impedance closer to 50 Ohm. Resistor is decreasing difference when impedance changes between buffer and track.☝️ And its only problem, when lenght is close to wavelenght of frequency generated by rising edge.
Robert, thanks again for another awesome educational and insightful video. You mentioned that oscilloscopes might not show correct results. This rose a question for me: Would you - or maybe some experts from oscilloscope manufacturers - be able to demonstrate the effect of a scope's capabilities on actual results of measuring noise when those measurements get difficult. i.e. at clock frequencies in the range higher than, say, 500 MHz? I'd love to see some "this works, because the scope has this and this capability" insights. I know I am dreaming here - but maybe there is something like this in your video pipeline? Thanks again! - Regards. Frank
Audio. I've heard a demonstration of a high capacitance cable used as a speaker cable. It sounded very different (calm) without loosing top end. It was proposed that this was down to the reflections being terminated via the capacitance. Any thoughts?
I thought you’d only get reflections when the line is electrically short and there is an impedance mismatch. In your case however I don’t think the line is electrically short. The ringing is caused by the the gate capacitance and line inductance. The signal was ringing at its natural resonance and was underdamped. Adding a resistor helped dampen the ringing. Another point, the frequency of interest here is calculated based on the rise time which is 0.6ns and it’s about 400MHz not 2GHz
hey robert, great video and crystal clear! The only thing I wanted clarification and further elaboration on was the length matching of the two branches from the aggressor trace. Since they are perpendicular to each other, why does making them the same length reduce the amount of ringing?
Because the signal reflects off of both ends, travels back and into the other branch. And if they have different lengths, the reflections arrive at different times, creating an oscillation between the branches. That's at least my understanding, but take it with a grain of salt, I'm just a hobby dude, didn't study it.
Can this be done inside the Altium tool? I have used Hyperlynx vs. Altium SI and I can't get the simulations to match. I wonder if you can show how to do it with Altium's SI tool.
The last bit of ringing on your VICTIM-IN trace is capacitively coupled edges from traces being parallel? Would a similar termination resistor on VICTIM-OUT remove that?
Hello, Robert! Why do you use 33 Ohm termination resistor? How do you calculate it? And what kind of results will be if use 22 Ohm or 51 Ohm insteed 33 Ohm?
What happens if you remove one of the input buffers so that that trace is left disconnected, for example if you had to remove a component buffer from the PCB but the tracks still exist?
Sorry for spamming, but I just got a thought, what if you add a 16.7R on PCB_tracks, and one more 16.7R on both PCB_branches? I mean, if you keep the rest the same as from the start, should that not eliminate any reflections?
The simplest thing to add in my opinion would be a capacitor, if it does'nt matter if the signal gets delayed a bit by the charging of the cap. Otherwise a full bridge rectifier would be a complicated yet good solution. I don't have any other ideas at the moment.
@@mzflighter6905 as close to the source of the signal as possible. That would only flatten one curve, the crosstalk would unfortunately still be there.
Please could you tell where are you running these simulations. Is it part of your Altium Designer or is it separate software and your importing your Altium project into this software
Long text about estimating output impedance if you don't have a good simulator at hand, its been very helpful at my work so i'd like to share:
It's hard to specify an exact output impedance of drivers since the resistance of the output switches (mosfets in our case) will differ depending on the drive voltage and such. Meaning that lower VCC levels will lead to higher output impedance.
If i recall correctly this is not a 100% accurate, but will give you a decent estimate of a drivers output impedance.
And as a general rule of thumb for LVC drivers specifically 20-33ohms are usually good.
If you change to a different family of drivers you will need to estimate their output impedance too, here is an example that has work well for me with numbers available in all datasheets (also for MCUs!).
Using numbers from the "Electrical Characteristics" table in the datasheet, find the output voltage section (Voh, Vol).
Under test conditions you will find the output current they used to get the numbers, for the parts used in the video (SN74LVC1G17) you will se that when driving low, when powered from 4.5V, with an output current of 32mA, the pin will read as 0.55V.
If you calculate resistance from voltage and current (R=V/I) you get this calculation: 0.55/0.032 = close to 17 ohm.
For high drive you will need to calculate the voltage drop inside the driver by taking VCC-Voh (4.5-3.8) = 0.7, which yields 0.7/0.032 = close to 22 ohm.
You can do this for the rest of the VCCs listed in the datasheet.
As mentioned before, its hard to give a specific number because the impedance comes from a complicated part such as a mosfet or bjt, but you get ball park values at least.
4.5V VCC:
drive high: 22 ohm
drive low: 17 ohm
Which makes a 33 ohm resistor good for a 50 ohm track because:
22+33 = 55 ohm
17+33 = 50 ohm
Both which are exactly or close to 50 ohm
2.3V VCC:
drive high: 50 ohm
drive low: 38 ohm
50+33 = 83 ohm
38+33 = 71 ohm
Not 50 ohm, in this case it may be better to not use any external resistance since the average output impedance of going both high and low should be 44 ohms. Or add a 6 ohm resistor to minimize both errors as much as possible.
Then again, the numbers we get from doing this calculation is not perfect, and if you do the calculations with numbers where VCC is the same but the output current differs you will also get different impedances (using Vol for the part used in the video, with VCC = 3V, 16mA output current is estimated to be around 25ohm, but with an output current of 24mA you get around 23ohms).
It's still worth doing the calculations though, since we have used drivers with around 75 ohm impedance at work before, meaning that any added resistance for a 50 ohm track only make things worse, so long as the resistance is not high enough to slow down the rise time enough that your trace looks relatively short verses your wave length again.
And STM32 micro controllers generally have 50 ohm output impedance when using "high drive strength" settings. So no added resistance there too if you are using 50 ohm tracks. You could also try using 20ohm tracks with the SN74LVC drivers, and you should have less issues too.
Thank you SO MUCH Tomas. Exactly what I was looking for!
Thanks for the information👍
Nice video and also tips about the impedance calculations. I used this idea recently.
It’s worth to keep in mind the Vil and Vih of the receiver together with the Vcc and series resistor at the output buffer. The voltage caused by the potential division might be reduced and may not drive properly. This is in the case you have a termination resistor too.
And you should consider the 32mA on the datasheet even if the output is connected to a CMOS high impedance input? This is due to the max current on the transition? Or this current is related with the load.
I have a project here with 22R everywhere, even on the output pins of the CPU. I will take a look is the datasheet days something about impedance on the outputs.
Thank you.
Excellent! I love these videos. They are very informative and educational.
Also, these kinda need to be long, you can't give such a thorough demonstration and explanation in 5 or 10 minutes. That's why your videos are excellent, because you take the time to actually care about what you are doing.
Thank you very much Manuel
I think 2 more improvements can be tested.
1. Tie victim buffer input terminal to ground.
2. Place decoupling caps to all buffers near the supply pins.
Thank you so much Robert. By the help of these videos, even we can not simulate our boards, we can visualize the signals while routing.
You are our hero thanks again :)
1) you mean like with a pull down resistor? When the reflection gets back, the netto resistance will be like a parallel resistor couple, while you need to be close to the line impedance. With a big pull down it appears like a open. In my opinion contributes to ringing.
2) what would the function be of the decoupling cap? Of course chosen correctly to prevent to act like an inductor, it would slow the rise/fall of the signal. And would act like a short for high freq signals. So act like a short and contribute to ringing.
It is just what makes engineering and the physics behind it interesting and worthwhile - the “Oh, wow, now I get it” or “That is great, even better than I thought” that happens for a blink of an eye.
I actually learn most valuable things from videos which incorporate these moments - because nothing is better than learning through (contagious) enthusiasm.
When Feranec thinks of something clever, or something he thinks is clever, he always looks at the camera with that evil smirk, it's hilarious. Lol
:)
Gotta love it 😀
The value of this video to me in its density of intuitive understanding of several complex ideas (high frequency signaling, the consequences of component rise and fall times, impedance matching, crosstalk), is so high that I think this is one of the best videos on electronics I have ever seen.
Unfortunately I cant understand the guy due to his accent.
@@leesweets4110 Fortunately this guy is multilingual, and you are the only one who does not "understand" that or him. I'm sorry for you.
Thank you for another brilliant video! I was just routing some i2s lines that go from an SPDIF receiver to a DSP when watching this. I was thinking about skipping the series resistor because I read somewhere that it didn't really matter that much. I'm very glad I watched this video, and my circuit now has length-matched tracks and series resistors.
Thank you MCUdude
Robert Feneral.... I want to thank you in a really big fashion... the input you provide is a huge help.... more engineers and TEACHERs like you that share their knowledge are necessary.... the best awards are granted to your level of commitment.... my best regards to you and to your company
Back in 2016 I was set to design a PCB with 16 pressure sensors hooked up to a uC over a single SPI bus on a distance of over 20cm. Clock 8/9MHz can't remember.
Whereas everybody was thinking of a noob project, I mean, 8/9MHz, how low is that 😅, I was already suspicious by intuition, not so much because of the frequency but especially because of the high fanout load. I got myself LT SPICE, took the rule of thumb numbers as 10nH per cm for the traces, don't remember for capacitance, and, for each input, the input impedance stated by the datasheet (roughly 1Meg and 10pF). Started the simulation.... we sat speechless in front of the transient analysis... It was clear it would never have worked without adequate considerations.
We added those series resistors here and there, tried various values and managed to eventually get a good signal integrity. 1st PCB release worked perfectly but only thanks to that simulation.
That's when I understood how critical things can be at even low frequency and remembered me, at the end, it's not only the frequency, it's the relationship of frequency and impedance ^^
Very nice example. Thank you for sharing RDS on.
Thanks for sharing your experience. As a fellow electronics engineer, I can confirm that if you want to do something right, it's totally worth spending the time and putting in that little extra effort at the early stages of prototype development. I've seen PWM signal distortion happening even at 100kHz! Signal rise/fall time, path length and grounding are key parameters.
@@elektrofreak-andg Absolutely. It is an often overseen one, the rise/fall time. And with modern digital logic, we also fell into that one in a project in 2011. Changed an old buffer (obsolete) for a "replace with" part. Didn't work anmore. What the heck... we got desperate... until 💡: what are the rise/fall times of the new one... Oohhhh, there it is ^^
Hey Robert,
Thanks for the video. It covers some of the basic SI principles and I'm glad you made this video because it can make my life as an SI/PI Engineer easier if someone like you is approaching something like this.
An important thing to mention that you did not is that the IBIS models allow you to also check how the signal will look like directly on the die of the component. Proper IBIS models have package parasitics, and pin parasitics (R L C) added in their models. This means that a signal might look good at the pin (where someone can physically measure with an oscilloscope) but at the die it can fail due to added inductance of the wirebonds and capacitance.
Hope this adds some valuabe information :)
P.S: I'm glad that someone finally explained why it's not all about frequency but about rise/fall times. I've seen 1MHz signals fail SI because they had 200ps rise/fall times and no terminations.
As Darko Obretan pointed out, the 2GHz wavelength in FR4 would be probably more like 80mm (3150mil) (?). I should use a different calculator, for example like this: www.pasternack.jp/t-calculator-phase-length.aspx
Good catch!
I think the 15cm wavelength is for propagation through vaccum (or air).
Great video once again, thanks! Regarding measuring this on your scope, it's not just about the scope bandwidth but you will need a good probe as well. My cheap 10x probes have about 15pF capacitance, at 100MHz. This translates in putting a load impedance of about 100 ohm (1/(2*pi*f*C)) on the line you are measuring. That should give you quite some effect already as you've now added a partial termination to the circuit!
Thank you Roel. PS: I agree about the probes
For me as an electronic engineering student, your videos are very interesting and informative. Greetings from Czech Republic.
Dakujem Vojtech
Дай Бог тебе здоровья, дорогой друг! Очень понятно объяснил. Симуляция просто супер!
Great Video !!!!
In my opinion U need to make it with respect to capacity and inductance ...
it is like Smith Chart by design of 50 Ohm line on the PCB, if Urs output is 18 Ohm U need to put some termination and to get 50 on line if the line out is 200 U need use Caps in pico to absorb this "energy" from going back but U changing this 200 to 50 in line of inductance and capacity. on the end of line.
In RF the One way is to make wider tracks to get more of pF just look for strip-line filters they 100% Use this technique.
This is such a good video, I'm really glad to have found youtube channels going into more depth on hardware development.
That's very interesting study. I have a couple of questions:
1) is the software validated, I mean which is the confidence level in the results. Software clearly show interesting "trends" but what about real measure of peak values?
2) I will be very interested in seeing a real PCB and repeat the same experiment you have proposed in this video. Can you do or can any on your follower do the test and share the plots?
Excellent information. Thanks you for taking the time to demonstrate all the permutations.
In many situations, where the rising/falling time is too faster than needed in the application,
slow it down by modifying the GPIO settings (configure output strength) or simply adding a small capacitor.
The critical length is significantly increased.
Would that work for differential pairs? Our for I2C?
Thank you Feranec. you are the best teacher I ever had.
For the output impedance of the buffer, since you have the IBIS model, put a 50 ohms termination at the ouput and measure the voltage at the resistor 50 ohms relative to ground on simulation. then uses a voltage divider equation and solve for the value of Rseries in the buffer. You can figure out the actual real part of the impedance. Then Zs of the buffer plus series termination should equal the transmission line impedance.
The reason for using 33 Ohm - you are trying to match the buffers output impedance to 50 Ohm, lets say you have a SN74LVC1G126, when the outputs is low, its parameters are max 0.55V @ 32mA = 17.2 Ohm output impedance. With 33 Ohm you get 50 Ohm :) This also means that this resistor value should be output specific, in order to get 50 Ohm output impedance. The resistor also needs to be placed as closed to buffers output as possible, so it appears as a single impedance.
But if the your sn74 output it's connected to CMOS input or microcontroller. The current will be 0mA due to high impedance of this inputs right? On this case you should use 50ohms? I did not understood why you consider the 32mA. It's due to the max current during the transition from 5V to 0V? Or due to the load current
Such a meaningful video for me. I almost forgot that it's the rise/fall time matters rather than the frequency of the signal. That's why I was surprised by the simulation results and think: why 10Mhz signal will cause reflection?? Thanks Robert :)
Great video Robert, my last PCB was so much better because of your wisdom, the next one will be even better!
Another good video. As my favorite Prof. (Prof Bogatin) would tell us, noise is all about the rise and fall time- aka the Di/Dt.
Slowly but surely... thank you Mr. Feranec. 👌
Would have liked to see this simulated in AD and compare it.
By matching the output impedance (driver + 33ohm), the reflection off the high impedance buffer at the end reflects back to the driver and the reflection is fully damped by the matched impedance of the driver to the 50 ohm transmission line.
Thank you very much for this! Its an excellent example of reflection which is not a commonly taught subject.
Great video Robert!
Thank you for sharing.
Impedance matching is the key.
It's unrealistic to expect such a short trace for most of ICs input and output on a complicated PCB, so short in/out PCB trace solution isn't a practice solution to resolve the noise issue.
Another great video by Robert. Thanks again!
Hands down this is your best video so far!!!! It shows how much we've all learned thanks to your previous videos. Really, really good one. Thank you, Robert.
There's one thing still bothering me, and it's your explanation as of why the dumping resistors improved the signal quality: was it really because you've got closer to the "magic" 50 ohms value, or was it because you've lowered the rising/falling time of the signal by creating an RC filter?
It was because of matching impedance. Resistance, capacitance or inductance: the sum matters.
Great job Robert, thank you for such an educational tutorial.
on 31:52 You mentioned that you believe one side matching is enough to remove ringing.
I know that a proper Termination resistor removes the ringing. But how to be sure if there is a termination resistor in high impedance buffer input?
It would be great if you make
a video about NanoVNA usage for impedance checking
or a video about how to design shields for noise immunity
Thank you Mustafa. PS: there is normally no termination on input of a standard buffer. Also, if there would be you need to be very careful as you may be creating voltage divider (depends on what kind of termination is used on output and what kind of termination is used on input).
Even if the the clock speed is only 10Mhz, the rise/fall times are 2 - 3 ns, meaning you need to apply RF thinking in the layout, i.e. trace impedance, via impedance, source and termination impedance, ground planes, via stiching etc.
As 4-layer boards are so low cost, using 2-layers for digital, would make reasonable tracks a bit wide on 1.6mm boards.
Someone may have already asked this, but could you get a close impedance match on the high-impedance input-end of the tracks by shunting ~50 ohms to ground at the inputs? Wouldn't that eliminate or greatly reduce any reflections? I ask because two of the three approaches here--the stackup thickness which would require more than two layers, and matching the length of branching traces--are not always practical (or at least not always desired for economy or size contraints). The work I do is limited to inexpensive two-layer, .0.063, FR-4 boards.
As always. Your videos are a GEM.
Fyi, if the input capacitance of the buffers gets large (say driving 8 or more buffers in parallel) you can improve the rise time of the signal at the buffer by placing the series termination resistor right in front of the buffer. In this case the track is acting like a critically damped RLC circuit instead of a transmission line.
You should also separate the two outputs from the drivers by some space to reduce the crosstalk. The crosstalk is proportional to the length the two traces run in parallel. The longer the parallel tracks, the higher the crosstalk.
oooooo man, loved it. That's a fantastic video/explanation.
Hi Robert. I want to ask some thing. At time 36:00 you calculating frequency from falling edge and it's time 0.5ns (1/x). This calculation is, I think, wrong. Or does it? Here is why: In one period, there is always 4 edges, 2 rising and 2 falling. Therefore calculation has to be 1/(0.5 x 4) to get right frequency 500Mhz and not 2Ghz. I verified this through on my system where I measured with my 1GSa/s oscilloscope, 2.6ns falling edge. I saw also ringing where I marked full period of sinewave and oscilloscope gave me 110MHz frequency which is close enough and this also supported my thinking. What do you think? Btw I enjoy your work. Keep going!
Correction:
Oh. I think now we are both wrong :) In one period is only 2 full edges (or 4 half edges). Therefore 1/(0.5 x 2) will be right. I fount also mistake on my oscilloscope where it calculates fall time from whole first voltage peak which is also wrong. Be this for everyone as warning to not depend on oscilloscope time readings of fall, or rise edges because this calculation can be wrong as much as bigger is first spike.
Very nice. Interesting subject and superb presentation/demonstration...
Presenting results with longer rise times and fall times is of interest.
Thank you.
as you see bevor 2 years age i saw this Vedio but i still seeing it ....Very informative Video
Dear sir your all videos are awesome really help full with correct information,
I just only says to you pls make your video part wise , pls don't make it longer thank 20 to 30 minutes. It will give you the maximum watch time. Maximum the revenue.
Very nice video Robert. Thank you for sharing this amazing content!
Thank you very much for the explanation Robert !
Thank you Robert! Really appreciate it!
21:39 Huh, I don't understand why we don't see any reflections from one BUF-INPUT onto another (and secondary reflections from forking point for that matter)
Great tutorial. Is there a way to know the impedance of the track based on the stackup in Altium?
When reflections are high on both ends, the signal can bounce around and you can have standing waves, and the length of the track will decides the modes allowed, when the length is short enough no mode will be allowed.
The "nominal" frequency number really doesn't matter because the signals are more like square waves and when you do a fourier transform on them a perfect square wave would have all frequencies (from 0 to inf), for real signals the rise and fall time will decide the fourier transform result and thus the frequency distribution. The only time when the nominal frequency is the real frequency is when the signal is a sinusoidal signal where a fourier transform will result in one point in the frequency domain, which could be the case in some RF situations.
Also I would keep the tracks further apart so that the H and E fields generated by one signal would have less effects the other track.
I just came across with this channel. Very interesting and clear information. Congratulations.
Hey thanks Robert! That was very educating
Very interesting and thorough explanation. Thanks, Robert!
Robert You are incredible
I saw some circuits where the designer use a zero ohm resistor in the pi antenna circuit.
As I understand those zero ohm resistors are zero ohm at 0Hz but at 2GHz the narrow path inside the resistor has a high impedance for a microwave.
A zero Ohm resistor is used if the antenna does not need tuning. The pi network is often included just as a precaution. You could also use a relatively large capacitor instead of the resistor.
Very impressing education showing us these hidden potholes in circuit design. for me the termination not only reduce the bounce back affect but it should also decrease the velocity of the output so that the first re bounce is not that strong as well i think. my first guess to your solution was to use resistors to reduce the ringing and also use ground plane to reduce the interference but I overlooked the length matching at first but that is rather obvious when you said it. I recall this length matching on boards was initially made to impedance match the traces but that they also serve the role to match the wavelength was less known to me so I actually learned something new here too. I have not built anything yet that works with this frequency but I do make oscillators that runs up to about 100khz or so and this generally won´t give you much problems that easy but I tend to use terminal resistors and also pulldown resistors to ground to reduce the noise between stages sometimes. but what I build is mostly control circuitry for amplifiers and powersupplies, timers and feedback or protection and mode indication stuff which I use for the tube amplifiers I also make for myself.
Please do the simulation with increased track width. You going to get pretty interesting result, caused by parasitic inductance of the tracks. So, it's basically a rule of thumb to keep whole stackup and tracks 50 Om matched.
can you give an example about how to do that ?
Hi Robert, interesting video indeed. While 2 out of three solutions were no surprise to me (impedance matching track and buffer output), the stub length matching was.
Maybe you could make a follow-up video going deeper into the signal split and stub length and explain better what happens there.
Funny things happen, due to different trace delays and splitting power at the 3 trace junction. Evey time a signal comes to the junction it splits into two signals 50% the power (same voltage, half the current).
Case with matched series resistor:
a) A=>J=>B1 (delay T0+T1)
b) A=>J=>B2 (delay T0+T2)
At B1 & B2 receivers the signals reflect going back (100% power, 0 Phase shift due to high impedence end)
aa) B1=>J=>A (delay T1+T0)
ab) B1=>J=>B2 (delay T1+T2)
ba) B2=>J=>A (delay T2+T0)
bb) B2=>J=>B1 (delay T2+T1)
Signals at driver have nearly no reflection (~0% power), but signals ab & bb reflect again at the receivers.
So signals bounce between B1 and B2 going lower and lower in power as the signals split and the ones going back to the driver are dissipated.
When the lengths are not balanced there are many echoes out of sync => high frequency oscillations seen in simulation.
In case of balanced arms the echoes are in sync, so lower frequency oscillations occur.
P.S.
Fun fact:
In flyby layout (no junction, just route thrugh/by on B1: A->B1->B2) there is a delay between B1 and B2 received signals, but also there is only one signal reflected and that one is finally dissipated in the driver series resistor:
A=>B1=>B2=>B1=>A
@@icestormfr nice explanation and it makes total sense. In a nutshell, it's about the reflected signals traveling between the stubs. but even if they are matched in length, the split of the reflected signals does happen. Maybe, additionally, in case of matched stub length, the reflections cancel (at least down the 2 stubs).
@@marcgoovaerts2614 yes and no 😅
They could cancel if one arm was open ended (high impedance) and the other shorted (low impedance) and the lengths balanced.
One reflected wave would have inverted sign (shorted end: incident wave and inverted wave add to zero volt).
When they meet at the junction the waves going back to the driver would cancel each other, but each wave going to the other receiver would still be there.
Oops, I was probably a bit too fast about my conclusion what happens at the junction when the two reflected waves from balanced arms arrive. Have to think about again, but could be that the waves combine without the extra reflection into the other arms 😅 (T junction Power Divide Theory)
Nice video. Thanks for saving me a future load of frustration :)
Awesome video thanks Robert!
Very nice video Robert!!! Thank you!
Great video as well as info. Could you pls post a video, how to calculate the resistor values for different signals like SCL,SDA,UART TX/RX etc.
Please make more videos like this!!!!!🙏🙏🙏🙏
Very useful content! Robert, your work is precious!
Great video, very informative! As always :)
The scope probe can add capacitance to the trace you are measuring.
Nice explanations of SI basics, the use of sigrity tools in your video is really cool as it show how things works. Also yo show how simulation evolve with change this is really a good idea to understand the feeling of physics behind. Thanks for your video, thanks for your clearly understandable english even for a french guy :)
This is great. Now i understand it 👍
The wavelength that matters is the wavelength in the medium (FR4), not the wavelength in vacuum (which is what you calculated). You need to shorten it by a factor of 1/sqrt(Er)
Thank you for providing such a great insight.
What about a Ground "GUARD - track", strip of copper added between the two adjacent signal tracks? That should also improve the situation.
Thanks a lot for this video! It is indeed very useful! You are a very good teacher! A question for you, would it be even better to add 50R resistor to your buffers inputs?
thanks again for this!
Very very good video and knowledge.
Thank you Robert, it was very useful. Will check your course in Udemy.
So shortly:
Lenght matching eliminates ringing.
Changing stack-up moves impedance closer to 50 Ohm.
Resistor is decreasing difference when impedance changes between buffer and track.☝️
And its only problem, when lenght is close to wavelenght of frequency generated by rising edge.
Great video, learned a ton without getting bored! :D Amazing! Great!
Great video! Could you please simulate with increased spacing between the input and the victim signal? I am just curious about the results.
Most probably only the blue signal will disappear from the picture, as there won't be crosstalk, but I'm also curious.
Robert, thanks again for another awesome educational and insightful video. You mentioned that oscilloscopes might not show correct results. This rose a question for me: Would you - or maybe some experts from oscilloscope manufacturers - be able to demonstrate the effect of a scope's capabilities on actual results of measuring noise when those measurements get difficult. i.e. at clock frequencies in the range higher than, say, 500 MHz? I'd love to see some "this works, because the scope has this and this capability" insights. I know I am dreaming here - but maybe there is something like this in your video pipeline? Thanks again! - Regards. Frank
Nice explanation..thanks!!!
Very important video, thanks for making this video 👍
Audio.
I've heard a demonstration of a high capacitance cable used as a speaker cable. It sounded very different (calm) without loosing top end. It was proposed that this was down to the reflections being terminated via the capacitance.
Any thoughts?
Thank you. Very informative.
I thought you’d only get reflections when the line is electrically short and there is an impedance mismatch. In your case however I don’t think the line is electrically short. The ringing is caused by the the gate capacitance and line inductance. The signal was ringing at its natural resonance and was underdamped. Adding a resistor helped dampen the ringing.
Another point, the frequency of interest here is calculated based on the rise time which is 0.6ns and it’s about 400MHz not 2GHz
Thank you so much for such great content 🔥🔥🔥
Because of your videos I learnt many things.
Thanks again
Very interesting and useful. Thanks.
hey robert, great video and crystal clear! The only thing I wanted clarification and further elaboration on was the length matching of the two branches from the aggressor trace. Since they are perpendicular to each other, why does making them the same length reduce the amount of ringing?
Because the signal reflects off of both ends, travels back and into the other branch. And if they have different lengths, the reflections arrive at different times, creating an oscillation between the branches.
That's at least my understanding, but take it with a grain of salt, I'm just a hobby dude, didn't study it.
Thanks for the video. Can you offer different simulation programmes?
Thank you Robert for your research work! What a role the wire capacitance has for this kind of distortions?
Can this be done inside the Altium tool? I have used Hyperlynx vs. Altium SI and I can't get the simulations to match. I wonder if you can show how to do it with Altium's SI tool.
The last bit of ringing on your VICTIM-IN trace is capacitively coupled edges from traces being parallel? Would a similar termination resistor on VICTIM-OUT remove that?
Hello, Robert! Why do you use 33 Ohm termination resistor? How do you calculate it? And what kind of results will be if use 22 Ohm or 51 Ohm insteed 33 Ohm?
I am wondering, what if you branch off at the source, and put damping resistors at the start of each branch?
it was very clear, thank you !
What happens if you remove one of the input buffers so that that trace is left disconnected, for example if you had to remove a component buffer from the PCB but the tracks still exist?
Could you make a "fly-by" topology please?
I also have to agree, what if you have a fly by topology?
I would expect no stub, no problems. But I can try that.
Very nice video, so interesting! Thank you
Sorry for spamming, but I just got a thought, what if you add a 16.7R on PCB_tracks, and one more 16.7R on both PCB_branches? I mean, if you keep the rest the same as from the start, should that not eliminate any reflections?
The simplest thing to add in my opinion would be a capacitor, if it does'nt matter if the signal gets delayed a bit by the charging of the cap. Otherwise a full bridge rectifier would be a complicated yet good solution. I don't have any other ideas at the moment.
Where would you put the rectifier?
@@mzflighter6905 as close to the source of the signal as possible. That would only flatten one curve, the crosstalk would unfortunately still be there.
Please could you tell where are you running these simulations. Is it part of your Altium Designer or is it separate software and your importing your Altium project into this software
Hello, your video was very helpful. I wonder, 33Ohm resistor is used to coordinate impedance with the 50Ohm trace, right? Thank you.
Doesn't Altium comes with signal integrity tool to simulate ringing?