Just gotta say, as someone who has gone through the universities and then into the industry. Your channel is probably the best channel for getting REAL practical application and useful knowledge for PCB design and I love how you present the simulations and use the extremes to show a point (i.e no via used vs the via fence - via fence not likely being realistic for an actual design I suspect but nonetheless proves the point quite fantastically). Appreciate what you do.
Wow, this just blew my mind!! I already knew and understood why you need stitching vias. But seeing it this way is just sooo interesting! It makes everything visually clear and straightforward. Thank you for this great simulation videos, you helped me a lot!!!
Try the coplanar waveguide (your fence) with minimal vias. This is typically how a coplanar waveguide is done and it would be interesting to compare the results.
You may also want to investigate how multiple GND/PWR VIAs on decoupling capacitors impacts their effectiveness. Also, capacitor physical size. Great series of videos, thanks.
Great video! Also I think that it is interesting to add that in a four layer stackup TOP-GND-VCC-BOT if you have a critical signal over top and you must go to bottom, then the stitching via to gnd is not what you need. A capacitor VCC-GND close to the via will do the magic. You must consider that the polygon of the VCC net in VCC plane (poly because more than one voltage is ussualy needed so the plane has cuts) is over the portion of the track on bottom. I propose a simulation of this case for a future video. Best regards!
@Digital Nomad If you have two or three different supply voltages your VCC layer is not a solid plane, therefor can't be used as a return plane for signals on the bottom layer. Therefor I put the signals on layer 3 and put the power distribution on the bottom layer. Other option is go for a 6 layer board.
I just stumbled on this video, two years after you made it. Better late than never! Great video. I didn't expect the huge improvement from the GND via fence, so it was very educational! Thanks!
Your videos about PCB design are just amazing! I have watched most of your Altium tutorials and they were super helpfull. Thank you so much for your great work. I really appreciate it.
Could you do an example with some serial bus standards? Like SPI or SD for example, I'd like to see how the traces intefere with each other. Great video Robert!
Almost every single video of yours, there is something new to learn.. great work Robert, not many schools teach these.. I really like insights derived from your talk with Eric Bogatin and Rick Hartley
Thanks for this. It's a very concise reference to point to, and makes what is technically complicated easy to understand. Not everyone has access to ADS, so I really appreciate this sort of content.
As always video was full of information, and today I learned something new about return currents because of you so thanks a lot. Keep sharing videos like this.
Great video! I would be interested to see simulations of different frequency signals and how the spacing of the stitching via effects the stray currents for the different wavelengths.
More, than 10 years ago, when i worked on military factory, old womens, which work's in P-CAD spoke me about that thing. They didnt have SIpro, only P-CAD and own soviet expirience in electronics. Today I started to respect them even more.
The simulation where you placed those ground tracks to completely shield the signal track is really cool. I remember when I was measuring cross talk between sensitive analog signals on an eeg amplifier, my senior engineer told me that if we use this trick in layout then the cross talk between adjacent channels will be close to 0. Thanks for showing me how that really looks like 👍.
The current penetrating to lower layer is probably visible this much because the color scale is saturated strongly in the upper layer. To see all values you could try logarithmic scale. I would be curious what is the actual ratio between the return current (density) on 1st and 2nd GND layer.
I think the reason for return currents to flow in other reference layers as well is due to the impedance of the return path. The reference plane directly under the signal will have the lowest impedance return path. But the subsequent reference planes will also have a return path impedance which is finite. The value of each return path is a function of frequency, dielectric height from the signal layer (as height increases, impedance increases) as well as the dielectric properties of the material and transmission line dimensions. You can think of each reference plane return path as parallel connected resistors (current is shared between resistors, but lower resistance values conduct more current). The first reference plane being Z1, the next being Z2 etc. So |Z1|
You deserve big respect. I got a question. You simulated only with ground planes but what about power planes? Can you share more simulations including power planes and ground pour at top layer?
Thanks Robert, visualization is always great, exceptionally the last slide that compare all of them. Other people have suggest great things to try. 18min is also good length.
Thank you for the wonderful simulation. just wondering, if you had done the same simulations with 1Hz signal or way upto 1GHz signal! if yes could you share the comparative slide? thanks for the share
Your recent few videos have been very eye opening (pun intended). I always learned what to do from other sources but this is the first time I'm seeing exactly why. Thank you for this series :)
Thanks Robert for the video. What I knew about these vias is that Altium has a tool called Vias Shielding, which allows you to create a track surrounded by vias so that it improves its characteristics. Greetings from Chile
Roberto, muchas gracias por el video, muy interesante, y simple, no necesitas saber más, una via cerca bien, 6 talvez para cosas muy muy especiales. Me quedo con eso. Saludos y gracias!!! te vemos desde LATAM también. Disculpen el comentario en español pero DOMINAREMOS el mundo no dentro de mucho, solo tenemos que resolver algunos temillas internos. jejejeje
love your content . you should do one on how to handle a separate digital and analog ground planes. Such as where to attatch them, should it be close to source or close to a sensor? what if you only have a single layer board (without a ground plane)
In a good design there is no reason for different "types" of ground planes (e.g. "digital", "analog") other than for galvanic isolation. See works of Keith Armstrong (e.g. www.emcstandards.co.uk/files/part_4_planes_corrected_29_june_17.pdf)
Congrats, very nice video, thanks a lot for sharing, just to clarify; it seems the worst case is when you have the stitching via far away of the track transition, seems to be worst than the case without stitching via.
Great simulation, thank you. Here is a question in my mind. Let's think it is a four layer system. Signal, Ground, Power, and Signal. How does the return signal look, and what are the possible solutions?
Adding the ground fence does add a lot of distributed capacitance, in turn affecting the input impedance of the line. That change in impedance will change how the input signal couples into the line. The channel host can correct me here, but ADS’s ports are probably set to be matched, so the input power was consistent in the two the simulation. Also, at 1MHz the change is probably small, but the simulation could easily give us that change in Zin.
Thank you for your nice video! Can you please how to import the PCB layout of Altium to Keysight ADS? I want to check my own PCB layouts with regard to the current path. And one more question! What is the difference between Ansys and Keysight ADS?
I think it makes sense that you see the currents following the tracks on the adjacent layers. The energy exists in the field between the signal trace and the reference plane, and that field is going to radiate outward a little - it won't be perfectly contained within the dielectric between layers.
Great series, Robert. It helped clarify a lot why some practices are done. In case you'd like to work on it, you seem to be pronouncing "Analysis" the same as "Analyzes" rather than /əˈnalɪsɪs/ .
Great videos, should see how those return currents affect cross-talk between lines. Even if two signal lines are well spaced, can a badly spread out ground current add noise? Can limiting the ground currents reduce EMI? Obviously, but how many vias will it take? A fun example, but something we should never do, would be a pwm signal next to an important analog signal line.
@@RobertFeranec I would be interested in seeing different current strengths too, since it is both frequency and current that define how big of a mess it will be
Very informative video. Really learnt a lot. I think you can avoid the return currents in the other ground planes be adding stitching via along the length of the trace and not just at the point of transition.
The return current is like a displacement current as well so depending on the distance between layers which can define the capacitance between the layers, the return current can flow on layer 2 gnd plane and layer 4 gnd plane when crossing signals from layer 1 to layer 3.
As far as I see at 4:50, you use an ideal source and 1 Meg sink for the simulations and also again it looks like you didn't calculate impedance for all 3 conditions (top to bottom, top to L3 and coplanar trace). What do you think that how those (impedance mismatches) effect the current density?
Thank you a lot for that Video and the effort you are puting into it. At the moment this is my most favorit TH-cam content and im looking everyday if something new was uploaded
I was rewatching this video now after watching your call with Rick Hartley, and I was wondering if you have the through hole connector connected to all planes or just the top signal and ground plane?
Great video Robert. What if the board is dissaminated with stiching vias? I know that Altium Designer has a feature to add stiching vias on all the board. Do you advise this kind of layout? And last: what's the difference between stiching vias and shielding vias? Thank you again
Can you please share the process with which you were able to import the design from Altium into Keysight's ADS software and how you started the solution? Please this would be really helpful as I need to simulate some Mixed signal boards I designed.
Dear robert, Thanks for posting your video. I learn PCB design with your videos. I want learn also keysight software how to convert then upload the PCB files in keysight then how to change the options. I need clear videos for keysight using please post a video
I really like these simulation videos to visualize what happens in different cases. It looks like care is taken to distill the example to really focus on the relevant concept. I'd be interested to see a video on ground pour sections that only have one via in them, or have a long "finger" that isn't stitched at the end. I try to avoid this on my designs, and fix it where I see it, but I'm not sure how bad it is, and how much time I should spend on it.
I wanted to see the last one without so many vias, because I think that the ground tracks on the same layer also were a improvement and would like to see it without so many vias only some at start end and middle maybe
Great video. Does the controlling the path of the return current also affect radiated emissions? For example, does a tightly controlled return radiate less than one with no stitching vias? Is it possible to simulate something like that?
Many thanks again for showing the beautiful simulation! Could you redirect me if you have shown somewhere the steps in ADS to do these kinds of simulation? Wishing to hear from you. :)
Thank you Robert for the great video. Could you do a video on impact of sandwiched signal (perfect strip line ) model VS one side Ground and other side split plane signal ? Thanks in advance
Appreciate your sharing. I'm curious about if the frequency up to 1 GHz and 10 GHz, does it still need so many stitching via to control the return current?
@@vejymonsta3006 I have not tried to simulate so high frequencies yet. I asked Keysight if I could play with their RF 3D field simulator ... lets see how it goes
Robert, I have a question regarding power planes.In my designs is the need to implement many of power planes across different inner layers, 4 or more ( For example L3, 4, 6, 7 ,8 with maybe L 2 and L5 , L10 as solid GND planes). Routing will be in X Y directions, so I need to continue one plane that is kind of x direction created on say L3, to got to L4 for y side creation. So I need lot of vias to change the direction, how much is depending of the current for the corresponding supply power net Stiching vias acts as "help" to create the fields for signal lines, OK so far, but here we have power nets, so DC. Do you see a need for stiching them too?
Very nice visualisation of why via stitching is so important. I do wish the simulation would show the field strength inside the dielectric, rather than just the current in the copper. At high frequncies, the energy is in the dielectric not in the copper.
Hi , Robert I am designing an RF chip antenna for my BLE application and I want to know how can I test the impedance matching parameters of the antenna practically . What instruments I can use? Could you please help me in this .
I think the real reason why adding reflow vias can improve the signal quality is that the electromagnetic field tends to propagate along the space between a pair of parallel conductors.
I assume you would have to have a certain average signal switching/frequency speed for this to matter. What frequency or frequency range was this simulation done? At what frequencies does it start to matter. Suppose I have a 3.3V digital signal that only switches at 50KHz worst case. Would it even make a different in this case? Is this only really for high frequency like RF?
Thanks for the nice simulations, It would be interesting If you did a simulation to see what happens when adding stitching VIAs in the case when the return currecnt flowed in multiple layers.
![เปิด อาณาจักร หมื่นล้าน "สาระตั้ม" l [Nickynachat]](http://i.ytimg.com/vi/3XE0nPF4YkQ/mqdefault.jpg)
Finally real simulations / answers from someone who designs real world PCB's! Thanks!
Thank you very much Danny
Just gotta say, as someone who has gone through the universities and then into the industry. Your channel is probably the best channel for getting REAL practical application and useful knowledge for PCB design and I love how you present the simulations and use the extremes to show a point (i.e no via used vs the via fence - via fence not likely being realistic for an actual design I suspect but nonetheless proves the point quite fantastically). Appreciate what you do.
Thank you very much
Wow, this just blew my mind!! I already knew and understood why you need stitching vias. But seeing it this way is just sooo interesting! It makes everything visually clear and straightforward. Thank you for this great simulation videos, you helped me a lot!!!
Thank you
gnd via fence is called grounded coplanar waveguide. It's used a lot in RF designs
Try the coplanar waveguide (your fence) with minimal vias. This is typically how a coplanar waveguide is done and it would be interesting to compare the results.
1/10 lambda spacing would be plenty enough. The amount of vias he used is a bit of over kill for the simulated 10k ~ 300M frequencies
You may also want to investigate how multiple GND/PWR VIAs on decoupling capacitors impacts their effectiveness. Also, capacitor physical size. Great series of videos, thanks.
Great video!
Also I think that it is interesting to add that in a four layer stackup TOP-GND-VCC-BOT if you have a critical signal over top and you must go to bottom, then the stitching via to gnd is not what you need. A capacitor VCC-GND close to the via will do the magic. You must consider that the polygon of the VCC net in VCC plane (poly because more than one voltage is ussualy needed so the plane has cuts) is over the portion of the track on bottom. I propose a simulation of this case for a future video. Best regards!
Thank you Santi. PS: I have this on my list to simulate it. Some other people also would like to see it.
TOP - GND - SIG - PWR is my preferred setup, normally have more than one VCC
@Digital Nomad If you have two or three different supply voltages your VCC layer is not a solid plane, therefor can't be used as a return plane for signals on the bottom layer. Therefor I put the signals on layer 3 and put the power distribution on the bottom layer. Other option is go for a 6 layer board.
@@sparqqling L1 and L2 are close together, however L2 and L3 have generally more than 1mm prepreg inbetween
@@RobertFeranec I am looking forward to this “with 4 eyes” 👀
I just stumbled on this video, two years after you made it. Better late than never! Great video. I didn't expect the huge improvement from the GND via fence, so it was very educational! Thanks!
Your videos about PCB design are just amazing! I have watched most of your Altium tutorials and they were super helpfull. Thank you so much for your great work. I really appreciate it.
Could you do an example with some serial bus standards? Like SPI or SD for example, I'd like to see how the traces intefere with each other. Great video Robert!
Thank you so much. This is exactly what I am looking for. I was wondering how a guard ring for rf pcb works. But I understand how it work visually.
You manage to clarify concepts that other people seem determined to obscure. Well done. Thanks!
Thank you C B
Thank you Robert for simple lunguage explanation! The latest simulation shows like you fence the signal like in coaxial cable.
Hello Sir, Could you make the same for differential pair signals..
Almost every single video of yours, there is something new to learn.. great work Robert, not many schools teach these.. I really like insights derived from your talk with Eric Bogatin and Rick Hartley
Thank you Srudeep
Thanks for this. It's a very concise reference to point to, and makes what is technically complicated easy to understand. Not everyone has access to ADS, so I really appreciate this sort of content.
Thank you very much VejyMonsta
As always video was full of information, and today I learned something new about return currents because of you so thanks a lot. Keep sharing videos like this.
Great video! I would be interested to see simulations of different frequency signals and how the spacing of the stitching via effects the stray currents for the different wavelengths.
I'd like to see a continuation of this video, where you sweep or step the frequency from VLF to SHF bands. If that's possible in ADS anyway.
More, than 10 years ago, when i worked on military factory, old womens, which work's in P-CAD spoke me about that thing. They didnt have SIpro, only P-CAD and own soviet expirience in electronics. Today I started to respect them even more.
The simulation where you placed those ground tracks to completely shield the signal track is really cool. I remember when I was measuring cross talk between sensitive analog signals on an eeg amplifier, my senior engineer told me that if we use this trick in layout then the cross talk between adjacent channels will be close to 0. Thanks for showing me how that really looks like 👍.
Thank you Nihar
The current penetrating to lower layer is probably visible this much because the color scale is saturated strongly in the upper layer. To see all values you could try logarithmic scale. I would be curious what is the actual ratio between the return current (density) on 1st and 2nd GND layer.
Wonderful video Robert. Return path is so important as you said and most of us do not consider it. Thanks a lot. Share a lot.
I think the reason for return currents to flow in other reference layers as well is due to the impedance of the return path. The reference plane directly under the signal will have the lowest impedance return path. But the subsequent reference planes will also have a return path impedance which is finite. The value of each return path is a function of frequency, dielectric height from the signal layer (as height increases, impedance increases) as well as the dielectric properties of the material and transmission line dimensions. You can think of each reference plane return path as parallel connected resistors (current is shared between resistors, but lower resistance values conduct more current). The first reference plane being Z1, the next being Z2 etc. So |Z1|
You deserve big respect. I got a question. You simulated only with ground planes but what about power planes? Can you share more simulations including power planes and ground pour at top layer?
very good simulation, nice and clean.
Thanks Robert, visualization is always great, exceptionally the last slide that compare all of them. Other people have suggest great things to try. 18min is also good length.
Big thumbs up! Very interesting video. I really enjoy these real life examples, explained in a way I can understand. You're a good teacher!
Thank you very much.
Thank you for the wonderful simulation.
just wondering, if you had done the same simulations with 1Hz signal or way upto 1GHz signal! if yes could you share the comparative slide?
thanks for the share
Your recent few videos have been very eye opening (pun intended). I always learned what to do from other sources but this is the first time I'm seeing exactly why. Thank you for this series :)
Thank you very much PS: It's the same for me ... that is why I am creating these videos
Thanks Robert for the video. What I knew about these vias is that Altium has a tool called Vias Shielding, which allows you to create a track surrounded by vias so that it improves its characteristics. Greetings from Chile
Thank you Leonardo
Roberto, muchas gracias por el video, muy interesante, y simple, no necesitas saber más, una via cerca bien, 6 talvez para cosas muy muy especiales. Me quedo con eso.
Saludos y gracias!!! te vemos desde LATAM también.
Disculpen el comentario en español pero DOMINAREMOS el mundo no dentro de mucho, solo tenemos que resolver algunos temillas internos. jejejeje
Great video! Thanks for serving this tremendously useful knowledge on a platter!
I really appreciate that you addressed the topic I suggested some time ago. Kudos!
Thank you Lukas
love your content . you should do one on how to handle a separate digital and analog ground planes. Such as where to attatch them, should it be close to source or close to a sensor? what if you only have a single layer board (without a ground plane)
In a good design there is no reason for different "types" of ground planes (e.g. "digital", "analog") other than for galvanic isolation. See works of Keith Armstrong (e.g. www.emcstandards.co.uk/files/part_4_planes_corrected_29_june_17.pdf)
Congrats, very nice video, thanks a lot for sharing, just to clarify; it seems the worst case is when you have the stitching via far away of the track transition, seems to be worst than the case without stitching via.
Great simulation, thank you. Here is a question in my mind. Let's think it is a four layer system. Signal, Ground, Power, and Signal. How does the return signal look, and what are the possible solutions?
The fence reminds me of a coaxial cable. Does it add capacitance that affects the signal? BTW thanks very much for these videos.
Thank you Roger
I would have to imagine so, you could see that those ground traces next to it in the final example had a ton of current flowing through them
Adding the ground fence does add a lot of distributed capacitance, in turn affecting the input impedance of the line. That change in impedance will change how the input signal couples into the line. The channel host can correct me here, but ADS’s ports are probably set to be matched, so the input power was consistent in the two the simulation. Also, at 1MHz the change is probably small, but the simulation could easily give us that change in Zin.
Wow robert. It is always such a treat to watch your videos... Thanks you.and please continue and inspire us more.
Thank you for your nice video! Can you please how to import the PCB layout of Altium to Keysight ADS? I want to check my own PCB layouts with regard to the current path.
And one more question! What is the difference between Ansys and Keysight ADS?
Excellent explanation. Thank you.
This was very helpful! Can you help understand how return currents are affecting performance?
I think it makes sense that you see the currents following the tracks on the adjacent layers. The energy exists in the field between the signal trace and the reference plane, and that field is going to radiate outward a little - it won't be perfectly contained within the dielectric between layers.
Great series, Robert. It helped clarify a lot why some practices are done.
In case you'd like to work on it, you seem to be pronouncing "Analysis" the same as "Analyzes" rather than /əˈnalɪsɪs/
.
Thank you very much Tom
Great videos, should see how those return currents affect cross-talk between lines. Even if two signal lines are well spaced, can a badly spread out ground current add noise? Can limiting the ground currents reduce EMI? Obviously, but how many vias will it take? A fun example, but something we should never do, would be a pwm signal next to an important analog signal line.
Some effects of crosstalk and coupling are visible in this simulation: th-cam.com/video/4nEd1jTTIUQ/w-d-xo.html
Like to see different freq down the 0mhz.
Good idea. I am making a note, I can try that in some future videos.
Agreed, seeing how various frequencies compare would be really interesting. Thank you for your videos Robert! They really are enlightening!
@@RobertFeranec I would be interested in seeing different current strengths too, since it is both frequency and current that define how big of a mess it will be
I found my new wall calendar's picture... (The one at the end of video !) Thank you a lot Robert
:)
Great video and many thanks for sharing. It would be nice if you also simulate the cases where 1 and 3 vias on the other side of the signal track.
great! It's easy to understand. I'll use many stitching VIAS.
Thank you
The two ground planes above and below the track are just two capacitors in parallel so the return current of 1MHz signal is on both of them.
Very nice to share all this with us, Thanks a lot. One question, is ground vias necessary for small signal (logic) ?
What is the program do you use for this simulation?
Very informative video. Really learnt a lot. I think you can avoid the return currents in the other ground planes be adding stitching via along the length of the trace and not just at the point of transition.
The return current is like a displacement current as well so depending on the distance between layers which can define the capacitance between the layers, the return current can flow on layer 2 gnd plane and layer 4 gnd plane when crossing signals from layer 1 to layer 3.
As far as I see at 4:50, you use an ideal source and 1 Meg sink for the simulations and also again it looks like you didn't calculate impedance for all 3 conditions (top to bottom, top to L3 and coplanar trace). What do you think that how those (impedance mismatches) effect the current density?
Thank you a lot for that Video and the effort you are puting into it.
At the moment this is my most favorit TH-cam content and im looking everyday if something new was uploaded
Thank you very much white test for very nice words
I was rewatching this video now after watching your call with Rick Hartley, and I was wondering if you have the through hole connector connected to all planes or just the top signal and ground plane?
Nice Robo. But try 1 stiching via at 100MHz with comparing to 1MHz. I think that next ground-plane current will be much lover in higher frequencies.
Thank you @Robert Feranec . I have question. how do u import your design from Altium into SIpro ADS?
Very simple and good explanation! Thanks a lot, Robert
very interesting and useful video. Could you make a video described how to insert stitching via in polygon?
very informative, especially the chart at the end!
Hi, very informative video. Can you try a video with a series component (AC cap) with and without void.
Great work as usual Robert! Thoroughly enjoy those videos
Thank you very much Bannay
Great video Robert.
What if the board is dissaminated with stiching vias?
I know that Altium Designer has a feature to add stiching vias on all the board. Do you advise this kind of layout?
And last: what's the difference between stiching vias and shielding vias?
Thank you again
Can you please share the process with which you were able to import the design from Altium into Keysight's ADS software and how you started the solution? Please this would be really helpful as I need to simulate some Mixed signal boards I designed.
Dear robert,
Thanks for posting your video. I learn PCB design with your videos. I want learn also keysight software how to convert then upload the PCB files in keysight then how to change the options. I need clear videos for keysight using please post a video
I really like these simulation videos to visualize what happens in different cases. It looks like care is taken to distill the example to really focus on the relevant concept.
I'd be interested to see a video on ground pour sections that only have one via in them, or have a long "finger" that isn't stitched at the end. I try to avoid this on my designs, and fix it where I see it, but I'm not sure how bad it is, and how much time I should spend on it.
Excellent visual demonstration. Is there a way you could do a video on a guard trace with simulation
I wanted to see the last one without so many vias, because I think that the ground tracks on the same layer also were a improvement and would like to see it without so many vias only some at start end and middle maybe
Best explanation, appreciate your efforts
Thanks for this simulation it is really useful
Great video. Does the controlling the path of the return current also affect radiated emissions? For example, does a tightly controlled return radiate less than one with no stitching vias? Is it possible to simulate something like that?
Great video! It might be interesting to see this with a differential pair.
Very good idea. I made a note about this. Thank you
Thanks Robert, a very instructive video.
The vias along the entire track is effectively creating a conduit/ coax feed of the track.
Hello Robert
Thank you for the video!
Could you please tell me what isthe tool you are using for the simulation?
It's called ADS from Keysight
Another useful video, as usual, your videos always make to learn something new sir, thanks for sharing your knowledge.
Thank you Haribabu
Many thanks again for showing the beautiful simulation! Could you redirect me if you have shown somewhere the steps in ADS to do these kinds of simulation? Wishing to hear from you. :)
Always best videos. Thank you again. I learn always with your videos.
Thank you very much Freddy
Thank you Robert for the great video. Could you do a video on impact of sandwiched signal (perfect strip line ) model VS one side Ground and other side split plane signal ? Thanks in advance
Appreciate your sharing. I'm curious about if the frequency up to 1 GHz and 10 GHz, does it still need so many stitching via to control the return current?
I'm also curious what each model looks like when you sweep the frequency from VLF to SHF.
@@vejymonsta3006 I have not tried to simulate so high frequencies yet. I asked Keysight if I could play with their RF 3D field simulator ... lets see how it goes
it took me a while to figure out 'written' current is actually a return current ))
Robert, I have a question regarding power planes.In my designs is the need to implement many of power planes across different inner layers, 4 or more ( For example L3, 4, 6, 7 ,8 with maybe L 2 and L5 , L10 as solid GND planes). Routing will be in X Y directions, so I need to continue one plane that is kind of x direction created on say L3, to got to L4 for y side creation. So I need lot of vias to change the direction, how much is depending of the current for the corresponding supply power net
Stiching vias acts as "help" to create the fields for signal lines, OK so far, but here we have power nets, so DC. Do you see a need for stiching them too?
Very nice visualisation of why via stitching is so important.
I do wish the simulation would show the field strength inside the dielectric, rather than just the current in the copper.
At high frequncies, the energy is in the dielectric not in the copper.
Thank you Nicholas. PS: I asked Keysight if I could play also with their RF 3D field simulator ... let's see ....
Another very informative simulation -- thanks Robert!
Thank you Graham
Thank you so much,Robert It's very useful.
Thank you for this video.
Hi sir can you simulate curved and miterd rf trace with coplanar waveguide . Which is better
This video is so helpful. Thank you!
How thick is the copper and PCB material, and what is the PCB material? FR4? What frequency is the signal on the track? DC? Thanks
Hi , Robert
I am designing an RF chip antenna for my BLE application and I want to know how can I test the impedance matching parameters of the antenna practically .
What instruments I can use?
Could you please help me in this .
I think the real reason why adding reflow vias can improve the signal quality is that the electromagnetic field tends to propagate along the space between a pair of parallel conductors.
I assume you would have to have a certain average signal switching/frequency speed for this to matter. What frequency or frequency range was this simulation done? At what frequencies does it start to matter. Suppose I have a 3.3V digital signal that only switches at 50KHz worst case. Would it even make a different in this case? Is this only really for high frequency like RF?
I am brand new to PCB. I want to start learning today. Where should I go?
Real simulation explains well :)
Thanks for the nice simulations, It would be interesting If you did a simulation to see what happens when adding stitching VIAs in the case when the return currecnt flowed in multiple layers.
Awesome, I Really need to this tutorial, can you introduce some useful books about signal integrity?
Thumbs up! Any chance to get opamp layout idea? Big thank you.
hey robert, for 13:37, it may occur because of image current. ?