Decoupling capacitors

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This video looks at factors impacting the impedance of the decoupling
network, such as PCB trace length, via selection, and capacitor parasitics.
The video also covers how current flows relative to the decoupling network
and associated power and ground planes. Let’s start by looking at the
decoupling network from a transient and AC impedance perspective.
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[@rickhunt3183]

The presentations from TI are always first class. Having some of the smartest people on hand to interact with makes this is a dream company to work for. That alone makes this one of the top 5 companies to work for.

[@darthvader3177]

This videos are really very helpful . Keep them coming ,thank you

[@longeron]

Very well presented and very useful information. Thanks.

[@guillermoherrera5771]

Excelente explicación saludos desde CD Juárez Chihuahua mex felicidades

[@BusyElectrons]

Very well presented. Thank you.

[@pravinsengottaiyan9244]

Thank you for knowledge transfer. Looking more videos.

[@rul1175]

Awesome content

[@dougli1sqrd]

At 7:57 the presenter says that typical ESL of capacitors is about 200 nH, and thus the traces inductance to a decoupling capacitor can "easily be a dominant factor". But the table shows inductance between 1 and 15 nH, nearly 2 orders of magnitude smaller than the ESL of a capacitor. Why does he say then that the trace inductance can be dominant, when the ESL is so much larger? Am I missing something?

[@dougli1sqrd]

ah so in the next slide the schematic shows ESL of capacitors to be around 0.2 nH. So I think he either meant 200 pH or 0.2 nH at 7:57 and he just misspoke. Makes sense!

[@edmondk8229]

Great video! Do you think filled vias make a difference?

[@arthurkay3151]

Filling vias should have a minimal impact on Inductance as the skin effect causes the high frequency current to flow on the surface of the conductor. It will impact the dc capacity.

[@gillsejusbates6938]

you can fill it with peanut butter and it wont make a difference

[@user-ww2lc1yo9c]

When you say parasitic capacitance at 11:00, what parasitic?

[@krish2nasa]

Informative. Thank you very much.

[@tfinmoraes]

Hi Art,
That is a great presentation! That is a solid starting ground (no pun intended) for a "lowish" frequency circuit layout. Thank you for sharing!
Particularly interesting that using multiple decoupling capacitors of different values can be detrimental due to same ESL. That really was a good practice back then when SMD was not widely available, so the usual 100pf || 1nF || 10nF...
Now, being picky here, at th-cam.com/video/3rxKZWQk_DY/w-d-xo.html, you mention that the trace parasitic inductance of decoupling capacitors is about 200nH, and can easily be a dominant factor compared to the parasitic trace inductance. But looking at the table and also at the next slides, I believe you meant the ESL of decoupling capacitors is about 200pF, not nH, right?

[@arthurkay3151]

Yes, I meant to say 200pH, not 200nH. You mentioned 200pF in your comment, and I think you meant 200pH as ESL is an inductance. In any case, I will do an update on the video to correct the issue. Thanks for pointing it out.

[@lucavassalli1564]

Thanks Art, you are speaking my language. www.empowersemi.com/wp-content/uploads/2022/02/impedence-vs-frequency.jpg

[@arthurkay3151]

Thanks for the plot! Good info.