3 Bit & 4 Bit UP/DOWN Ripple Counter
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- เผยแพร่เมื่อ 1 ต.ค. 2024
- Digital Electronics: 3 Bit and 4 Bit UP/DOWN Ripple Counter
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To simplify the circuit: Use an XOR gate it will give the same output.
and use Tff insted of jkFF
@Pooja Agarwal no you can't use exor here cause exor needs two same literals but here they are three so you can't implement that here get it ! 😉
@@nikhilhaspe2734 could you explain further? i don't see a problem with using M XOR Q as one of the 3 literals is just complement of another...
@@aditwani6562 ig cuz we're trying to physically use Q' instead of Q as our clock in down-counting, XOR would mean dono case mein Q see hi karenge
Obviously
this guy is saving my life each time!!!
Mine too...
Nigaa true
Yeah ......;-);-);-)
@@ankita_chavan.
Yes
how can you say this he has not told from where the output will be taken
You could've simplified the circuit a lot more by using Qa, Qb etc as the next flip flops clock and used a 2:1 MUX to select the output between Qa and Q'a and so based upon the select input M.
Can MQ'+M'Q circuit diagram with AND/OR gates be replaced with a simple XOR gate?
@@medicharlaravivinay9591 Don't misguide people q and q' are always opposite, that is the rule of a flip flop. A mux or a xor can replace this circuit
ya , i think it should be replaced by the XOR gate.
Yes
Yes
No we cannot use because see the 5th state in the truth table where M=1 and Q= 0 and if you XOR both the output is 1 where as it should have been 0
why not just use a 2x1 MUX?...... where M will be the select line and Q and Q' will be the inputs
yup, you can,
That is actually a 2x1 mux expanded in terms of gates. Draw a rectangular box over 3 gates and you get the mux.
Rather use a xor gate. Much simpler
Nerdiiezzzz
Where is 4bit??
How can Q and Q' both be zero or 1 simultaneously 3:21
same question
instead of AND-OR logic, we can simply put Ex-or gate( M and Q as inputs)
The presentation is awesome, Thank you. Just two things, you could have used an XOR gate to avoid the mess and also you didn't point out the output.
It felt like this was rather incomplete, what was the output in this case? I am guessing if it were up counting it would be just "Y" for each bit, and " Y' " for down counting. Yet is there a way I can store a number in a counter and be able to both increment and decrement it according to my needs :D? (I feel like what you just did will do the job but still can't see it clearly) Thank you for putting all these videos for us.
why not use a 2:1 mux in the combinational circuit part?
Yes !
in the table,which you made, how can Q and Q complement have same value..e.g 1 and 1 or 0 and 0???
+ABHISHEK KUMAR mportant question sir plz ans this question
take them as not used/don't care.
This is really bothering me.
there won't be a case when there is 1 1 on both the outputs because we are feeding 1 1 as the input to the flip flop and the output generated by this combination gives the previous state which can't be 1 1. The truth table that is creating this confusion shows merely the possibilities but it doesn't necessarily mean that there should be 1 1 as the output.
Yes
Learning things is far easier than the college teaching ❤️
Thank you so much neso academy for the lovely videos
1)simply use a 2:1 mux and a common mode line as combinational ckt.
2) u can't get all possible combination in M,Q,&Q(bar) table because Q & Q( bar) are always complement of each other as u using jk(1,1 state)/T ff.
3) collect the output as Qa, Qb, Qc. when M=0 u'll get up counting & when m=1 u'll get down counting (in conventional way).
I like your idea of using 2:1 MUX and I also thought about these combination in which cases Q and Q' are same.
Thank you for your comment.
@programmingShorts2022 yes
We can simply use XOR operation (M XOR Q). Lets say, for M=1 we want to do down counting and for M=0, we have to do Up counting. Then, clock of Q1=Q0 XOR M. when M=0, clock of Q1=Q0 XOR 0=Q0(which is the condition of up counting) and when M=1, Q1=Q0 XOR 1= Q0 COMPLIMENT (which is required condition for down Counting.
How can Q and Q' be equal in some cases in the truth table ?
The use of XOR instead of AND + NOR gate (which is a 2 to 1 MUX) is logically correct. However, you need to consider loading at outputs of the flip flops, Using only Q output with XOR will have uneven loading and hence rise time will be different from fall time. This produces duty cycle != 50%. It can cause issues at higher clock frequencies.
Got in love with electronics after seeing ur videos😍
Sir how Q and Q' can be same when you made truth table of 8 combination m0, m3, m4, m7 cases should not be there kindly explain this
Sir in the M Q and Q' table, there are two cases (namely 011 and 111) when Q = Q'.... But then Sir how is that possible and allowed in a digital circuit to occur ?
Sir, why can't we use M XOR Q.
Instead of that combinational circuit
Very good and informative videos, really relieved from some of the stresss..... But, HOW IS THIS GUY USING HIS MOUSE SO SMOOTHLY???
U have done a mistake 5:55 in k map equation ... its :- MQ+M(BAR)Q.
U have written :- M(BAR)Q + MQ(BAR)
شكرا @Neso Academy
correction needed, q and q complement can never be same as shown in table.
sir in the M,Q,Q bar table the combination where Q=1 and Q bar=1.....how it is possible?,can u tell me abut it sir please!!!
what time sir?
exactly.
2:39 sir
The Truth table u made in the beginning to figure out the circuit structure to be inserted in between flipflops had # columns M Q and Q'. and u have considered the entry where both Q and Q' is 1. which is impossible because Q and Q' can not be 1 at a time. But it dint affect ur final circuit because Q=Q'=1 is a dont care condition and u can count them as 1 in ur k-map. But u should rectify that
yeh accactly
Don't know whether it's correct or not
But even 2×1 multiplexer is an alternative
The way of explaining has made understanding concepts effortless.
In combinational part why are you not using XOR??
There is a problem with this circuit, sir.
If the output of the combination circuit is high when the mode is changed, the next flip flop will register that as a falling edge and change state.
This design can only switch modes reliably while in the 000 state.
In other words, you cannot count up 0-1-2-3 then switch modes and count down 3-2-1-0. That mode change will trigger flip flops B and C and change state, and the resulting number will be 5.
This is fine, if that is the intended behavior, but you may want to disclose that.
so i built this circuit in multisim, and it turn out that when m is 0, you have a down counter (the bits ripple through to make 111 from 000 initially) and and when it's 1, you have an up counter. I made this with XOR gates instead of the AND/OR logic you implemented but the function was the same. just wanted to clarify if anyone else comes across this. Thanks for your videos, I watch all of them religiously
When q ' is connected to clk. It will act as up counting . There is nothing flaw except that.
Hello , thank you so much for this ! i was wondering though , what about the outputs , shouldnt we make a line going from Q a,b,c so we can show the result of the counting ?
Sir, I want to ask how can you list the true table that Q and Q complement have the same value?
for MQQ' == 011, y should be X, since this condition never happen so should take as don't care for small output(Y) logic
I have the same doubt
Can we use 2*1 MUX to select from Q and Q' ,M as a selection line . if M=0 Q is selected , else if M=1 Q' is selected ?
Yes that is right as well.
Your explanation is very good. I think we can also use also Multiplexers instead of the gates, can't we?
Sir, where we take Output of this circuit?
Qc Qb Qa is going to give output I guess
@@hemanth6225 yes
Where is the output ?
just use a MUX
+Murad asaad nice idea
+Murad asaad ikr i had the same idea , don't know why he isn't using it
Sir how can Q and Q' be same? There are 4 combinations in which Q and Q' are same at 2:47 in the table. Please can you explain how that is possible
It cant be the same XD, Even if u draw the truth table without Q' u get the same expression 😀
Thankyou
Useful even in 2023
Design a 4-bit ripple up-down counter with two control bits C and D. The circuit
counts up when the control variable C is logic ‘HIGH’ and counts down when C is
logic ‘LOW’. The circuit will work only if 𝐷=1 and remains unchanged if 𝐷=0 ...????
In finding the relation for Q and M why did we consider one of the inputs like 0,0,0 and 0,1,1 .I mean if we consider Q and Q' they are not supposed to be same na ?
I feel using a 2:1 MUX between all pairs of consecutive flip flops would've been better, taking control input M as select line and inputs being Q and Q' of the previous flip flop and the output being fed as clock to the next flip flop.
Timing diagram 🤕
why cant we just xor gate with m and q as the output is that only...????
I was asking myself the same question
We can use a multiplexer in between ever flip flop pair with Q and Q' as input and M as select line
Loadss of respect to neso academy n THIS PERSON , brother 🤝🤝🤝
for MQQ' == 011or 111, y should be X, since this condition never happen so should take as don't care for small output(Y) logic
The circuit would have been more simple if 2:1 mux was used as choosing circuit.
Can we connect Q' to CLK for M=0 while designing combinational circuit
can we use xor gate here.
yes exactly, in my college book it uses XOR gate.
yes exactly, in my college book it uses XOR gate.
yes exactly, in my college book it uses XOR gate.
one more reply would be amazing
one more reply would be amazing
Q and Q compliment are always opposite to each other then how he took Q and Q compliment this way?
what is logic 1 representing? thats not a Hi or Lo signal right because M and `M are the lo and Hi signals in this scenario, so what is running into J and K?
Upcounter means Q bar ,down counter Q needs to give next ff??
how come in the truth table q and q' have same values........????
Can't we use a XOR gate??? It will simplify things
He always revives me
Same as in freefire😁
terima kasih banyak
How did u write q=0, q'=0 and q=1,q'=1 in the truth table?
This guy help me to become a Topper
Q and Q' are opposite to each other right then how 0,0 and 1,1 case will be there in the table??
Why not we take 3 bit down counter example 1 as it can have both 1 and 2 seprately
Why not just use the XOR gate? Less wires and components.
why Q and Q quer can be both 11? is this allowed in normal FF?
I think the inputs are wrongly taken. When q is 1 q bar cannot be 1
Why can't we use 2:1 MUX in the mode control ?
AMAAAZINGLY described :D
4 bit asynchronous up/down counter ka truth table kaise banate hai
isn't the combinational circuit used in this counter equivalent to a 2 X 1 MUX ?
Cant we use a XOR Gate M^Q
yes u can and its ok if not but in the question it said to use minimum amount of gates as possible just put XOR
Even I had the same doubt! 👍
No you can't, check the truth table. M exor Q doesn't give out put as Y
@@mohitthorat8580 it does give the same output
Check the 5th entry of the truth table, 1exor0 should be 1. But o/p is 0.
my though power is dead its very diffcult
USE M and Q Xor and instead of jk use T flip flop
If Q is 0 Q complement cannot be zero how it is possible
basically we have to use mux? right?
Use multiple etc fine but op where to take???
This can be a good exam question.
Well, actually you do not need to add Q's complement to table since it will be always opposite of Q. When you do it with only M and Q you can use just a XOR gate as combinational circuit.
+Fatih Erdem Kızılkaya circuit diagram plz
why we not used Y=M (XOR) Q between the two flip-flops in up/down ripple counter
+Shailesh Pawar you can use
but it is best way so that people can understand
Can we use XOR gate instead of two ands and one or at 7:45
Couldn't we use just an XOR gate instead of two and gates
Why didnt you use an Ex-or GATE.
And from where we are going to consider the output
Why not use exor gate as a combinational circuit
SIR
IS UP/DOWN COUNTER IS SAME AS TRUNCATED COUNTER
here out puts are QA,QB,QC............................
Hi guys, as positive feedback, I have tested your circuit, but both mode perform a down counting only. For 2 BITS counter both mode count: 11, 10, 01 and 00. I think you should revise your circuit. For 2 BITS up/down counter, please look carefully that output Q of 1st T flip-flop must trigg the clock Pulse for the second flip-flop since this is a typical of asynchronous counter. Then, the output Q and Q' of first FF must be chosen using 2 to 1 mux then we OR both and take the output of OR gate as one of it output bit itself (Verify MSB or LSB. Do the same step for the second FF, third FF and fourth FF for 4 bit up/down counter modulo 16 from 0 to 15. Thank you.
for the combinational circuit.....instead of using 2 AND gates and 1 OR gate, why can't we implement the combinational circuit using a single XOR gate itself?
Because the equation is as (NOT(M))(AND)(Q)(OR)(M)(NOT(Q))=M(XOR)Q
Why are Q and Q' both same in our truth table?
I need ripple counter then decoder then a 4 bit integrator making 4 triangles faseshifted 180 degree, the clockpuls coming from a integrator osc circuit making a puls. thanks.
As the outputs of flip flop are complement of each other ....
Why did you consider the case where q and it's complement is equal..While making combinational for.
Here is the contradiction.That is even if there is down counter which is Q',the next ff uses the Q as clock .But according to selection logic,it uses Q' as clock for next ff .This congufuses me .
for up counting we need to feed QA_bar as clk to next flop right so if it should happen at m=0 then function would be M_bar.QA_bar + M.QA . So Finally we need to use M xnor QA
Sir fir 4 bit me kitni bar count krna parega ...i means 0-15 bit leni hogi
Aur agr esa h to synchronous me apne 3 bit k lie b 0-15 combination use kie the ...??
Plz sir esa kyu hua bta dijie
kavita indre just add one more flip flop..and everything will remain same as previous
in that case what will be the truth table?
I have a doubt regarding truth table F(M,Q,Q') how the Q & Q' will be same eg: at (0,0,0).. practically Q and Q' is not possible.
amazing. (Y)
another way to do this one is to use 3 xors at the outputs than 2 xors at the clocks:
use output_a as (m xor Qa), output_b as (m xor Qb) and output_c as (m xor Qc) - this comes with advantage of not having clock cycle shifted by 1 (see previous video)
Thumps up those who watch neso academy before 1 day of exam in 2X mode to cover syllabus ,and save their life
sir but where are the binary outputs???such as ..there were in up and down counters.......???individually
Why we not use xor gate as the combination
is this also called as Mod Counters????