3 bit & 4 bit Asynchronous Down Counter
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- เผยแพร่เมื่อ 1 ก.ค. 2024
- Digital Electronics: 3 bit and 4 bit Asynchronous Down Counter
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Watching this during the Corona Lockdown, when there are no Uni lectures and i was feeling totally lost! man thank you so much.
Same bruh
This is not lockdown time and I am still watching
@@saurabhgairola9145end sem😂
for the second configuration a separate state table has to be made as the outputs are now changed. In 1st configuration they were in complement form i.e. Qa' Qb' Qc' but now in 2nd configuration they are as Qa Qb Qc . And while you analyzing the values of Qa, Qb, Qc i.e. output of 2nd configuration ( 8:29 - 8:37 ) you have compared it with the 1st configuration state table which making all the confusion in the audience.
4 saal beet gye hai tumhare iss comment ko. Ab tak toh tumhari job bhi lag gyi hogi ?
@@pronoob4890 haa bhai 😅
@@keshav_c17 kaha job karte ho?
Aur iss question ka answer bhi bata do…
@@keshav_c17 super senior 😁🙇
@@pronoob4890 aab tak toh tumhari bhi lag gayi hogi mujhe v clear kara do yaar😂😂😂😂
In the second circuit , set values of qa' qb' qc' as 1 initially and analyse qa qb qc accordingly .
Thank you sir for making video with great explanations.
for down counter consider from pulse 1 as it gives decimal 7... continue till 8th pulse to get 0. pulse 0 is not considered as we assume all flip flops to be in power down state (no memory stored so Qa, Qb & Qc are 0 initially) 0th pulse is same as 8th pulse
The best explanation i have got on counters so far
In the second configuration, why did you start taking ouptput from the secomd clock pulse , and not from the initial state like you did in the first configuration?
Coz first output will be the same in any condition
i dont know how best i can thank you for this great lectures. please you have been using negative edge flip flop, if its positive edge, what will be the timing diagram?
It is also possible to use positive edges instead of negative edges in a up counter to turn it into down counter.
yes
Yes for that we will use Qn as clock as well as output
@@mihirvora391 Well I've already graduated but thanks for reminding me what I went through lol
@@FatihErdemKzlkayaiam going through the same
@@anirudhani8160 Good luck brother, you'll make it through. Enjoy those times, do not stress over it too much!
Sir in the waveform diagram of down counter it looks like it is positive edge triggered rather than negative triggered. But you had said that down counter is negative triggered as well.
we can also use positive edge triggering
thanks for your great effort
Sir, You are my life saviour! The word thanks is not enough to show my gratitude..
Show your gratitude in cash
sir u are great....i like the way u explained...thanks a lot..
Awesome lecture series ❤
Thank you for the video. Great job you have done. But as far as I can see these two methods don't have the same result. In the first method initially it is 111 (as the compliment of 000) and that is fine, but in the second method we have 111 at the first impulse, and initially it is 000. Please comment.
It' not 000 it's 100 anyhow it's not equal to 111
Everything that is concievable is clearly stated. Geat job.
sir in second circuit what u considered initially is zero Qa=0,QB=0,QC=0 fr initial state
awesome lecture, thank you!
I dont understand in the second circuit you are complementing Qa prime before feeding it in the clk of Qb. So is that not the same of feeding Qa in the clock of Qb? does that not make it positive edge triggered?
Thank you very much!
Thank you for you videos...
In the second configuration of the 3-bit up counter where you feed the negated flip flop output, why do you start the counting from the 1st clock pulse?? why do you not assign the value for the initial clock pulse??
The system is driven by Qa', Qb' and Qc'. There's an offset of one waveform to get all of these into zero state. Once that happens, it's just mimicking the first configuration.
Rahul Madhavan How does that answer his question? You've answered what happens after the max count which is way different than the OP's question which asks why the initial clock pulse is not considered?
@@ir2001 I would suggest that you observe the waveform diagram for the second circuit , the starting point is actually after the first timeperiod because the first wave is the end of the last wave
Difference between up and down counter??
Does it depend on if we are giving logic state high or low??
sir,
it is necessary to show second circuit condition on waveform ???
just awesome sir
Thank you !
in the second circuit the graph or truth table follow the downward counter for complement outputs but how can you get the downward counter from not not complement outputs?
THANK YOU so much sir
If I want Q as output and Q only as a clock to nxt Flipflop then down counter be achieved using positive edge triggered clock.
It's only mandatory for B and C
A is independent of it
sir did u had inverted the o/p? in both of the configuration
In my text book, the down counter operates with Q1=Q2=Q3=1 at the initial state, not the complement of them equal to 1 (in which Q1=Q2=Q3=0, this is the initial state of UP counter). Hope you check it again.
And anyway, you’re doing God’s work, keep it up. Thank you.
please explain
well, the initial state of the DOWN counter, even if you take it as the complement of the initial state of of the UP counter (Q1 = Q2 = Q3 = 0), will be Q1 = Q2 = Q3 = 1, which is the correct initial state.
what happens when the 8th clock pulse edge is applied i mean does the counter go back to 111 ?
In the second circuit ,initially we are taking 000 but initially there 010 because clock of second flip flop is already 1 as it is connected to qa complement which initially is 1 as qa is zero initiaally .pls explain
you can use the up counter with positive edge triggering for down counting.but the initial state will be 0 and then it starts down counting from 2^n - 1.n = no of FFs
if you use the second method that sir told, then too the first clock pulse is 0 and downcounting starts from 1st pulse
What happens if both the output and the clock to the next flipflop is taken out of negated output of flipflop? It still gives down counting right? Thanks
Bro ur god during exams
oh may God ,lol.
Thank You Sir
Just one suggestion.. Plz try to always tell about the next presentation topic so that it is easy to follow the lectures.. Coz youtube sometimes doesn't show the next video.. Or you can either number your videos.. That would be even better.. Nice work btw.
just open the playlist
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@@sainimohit23 yup
@@Pra_gyaPandey OMG I used to watch videos of NESO academy lol
@@sainimohit23 haha 😂
Thank You, Great Videos, Nice English.
Hey buddy. You are awesome man. Just splendid.I have completed a chapter from your Channel. I will be grateful to you vai.I am a Student of class Eleven. From Bangladesh 🇧🇩🇧🇩🇧🇩.
Love you😘😘
please upload Analog electronics video too.
here we are considering before first clock pulse Qa as 0 (zero )
what if it is 1 from initial ?
Thank you so much sir 😊
Man you are awesome
for -ve edge trigger please explain the waveform for down counter without taking up counter compliment,
Thank you sir
Dear Neso Academy, can you have a lecture video about asynchronous system: how to make the flow table, how to reduct the state through partitioning and using merge diagram. Or an example problem like vending machine?
I hope you can help me.
Thank you.
thank you very much
At 8:20 you're reading 1,1,1 from the 1st clock pulse (triggering) but writing it down after initially in the table. Why is that so?
since it was a down counter
please help as to how in the second circuit u start taking output number 1 after 1st clock pulse and u don't take the initial state 000 into account..as you have done for other counters
same question here.
This is a down counter in which we count in reverse order. In the previous videos sir explained us UP counter in which we start counting in sequential order (000, 001 etc.)
well you all from assam..Hello.In the second circuit the clock values are taken as complimented so
@@alikhanmehboob610 that does not ans the question.
don't we need to take preset for all flip flops in the second diagram? then only all the outputs would be high for first clock pulse right?
i have a doubt.in practical experiments,how do we connect preset and clear to ic chips in a bread board
How did we get graph(rise/fall) for the last Qc?
in 2 nd method of down counter, for making waveform of Qc, can it is not follow the compliment of Qb of the previous method??
thank you
which circuit gives efficient design sir ?
What will be the output if i take clock and output both as complemet (Qa,Qb,Qc)
i will contribute to you once i will start earning thankyou soomuch
loved it...Nice content..
ur videos are very helpful.
In the second configuration of the 3-bit up counter where you feed the negated flip flop output, why do you start the counting from the 1st clock pulse?? why do you not assign the value for the initial clock pulse??
I had the same question, but it's the same thing really!
You will start with (000) then (111 ) so you're basically going backward
I have a question that why don't you use positive edge triggered FF's, can you pls explain!!
thx for the help
Can i design a mod-5 asynchronous counter without using CLEAR Pin? I may use some sort of combinational circuit.
Please Reply
Life saver before the exam ...
Clock is negatively triggered or positively trigvt
can we use T flipflop instead of jk to logic -1?
Do I need to show both original outputs(i.e QA, QB, QC) and the complement of the outputs in the time diagram?
If you draw the second one it is necessary but if draw the first circuit it isn't necessary to draw at all.
in the second config the counting starts from 000 then 111 then 110 and so on ....
Can you plz explain for up and down by using d flip flop?
For 4 bit down counter ...t flipflop use or j k flip flop??
for the second config isnt it initially 000 ?
thankyou dude
sir why you made 3 flip flops in 3bit and 4bit synchronous down counter??
Was there a 4bit down counter diagram??
I didn't notice any, please provide timestamp.
No one can beat neso academy in terms of detailed explanation
thank you sir :)
I don't understand it can you explain it for the down counter for 4 bits?
Fantastic
Pls upload any asynchronous sequential ckt problem
but sir u use initial stage for 7 in first circuit and in second circuit u use first falling edge to show decimal 7 ?????
Using second method we have 000 initially and 111 for 1st falling edge, and we should consider initial pulse which makes the answer wrong. Someone please help me clarify the concept.
What u said is correct its first coming 000 🥲
please done something with d-flip flop
Down counter’s wave form wrong , u have to take Qb on the bases of Qa’ and then u have to take Qb’ but u take Qb on bases of Qa . Am I right or wrong
You making it simple...
Sir why u r not taking the initial values while calculating Qa,Qb, Qc for the 2nd ckt....pls solve this
Sir the title was down counter but you drew the table for up counter I didn't get it
what is logic 1.how do we connect it while wiring ic chips
He just means that a high voltage is applied to all of the inputs (a logical "1") as opposed to a low voltage (a logical "0"). In terms of practically wiring up IC chips, I'm not sure how it's done -- I believe you have to select two voltage levels (no doubt based on the parameters of the chips themselves) to serve as the "low" and the "high" voltages. Hope that helps a bit!
How to pause and hold count
can u start with 2nd configuration 1st , 1st one is easy to understand but 2nd one gets messed up with 1st one ?
Mention msb and lsb for second configuration please..
Qa=lsb and Qc=msb
Best sir👌👌👌💐💐
Can't we take the output of the complement when complement is given as the clock?
Sumangal Saha No we can't because then it will become upcounter.
I thought i was the only one confused at last but theres chaos in the comment😂😂😂😂 Plz someone help me to understand the last part
In the second configuration of the down counter where we feed the negated flip flop output to the other, how do we start at '111' when Q_A is 0 initially?
+and1fer I'm sorry if it took 6 months to see to your question, but QA is zero, and we're using QA' (the compliment) as the input therefore of course its 1. because when you compliment 0 you get 1.
lwfabsman No he's talking about the logic 2 where the clock is different. QA is 0 there initially.
lwfabsman but i want to kno for the second circuit , here we take qa,qb,qc not the compliment and it should start with 000??
@@utkarshgangwar8125 my friend its starting with 000 and the next state is 111,110,101,100,011,010,001. After that it again goes to 000. In that way we get the downcounter logic. Next state of 000 is 111. Here logic is same don't confuse with what you get in the beginning.
I was experimenting. Used same up counter, but with positive edge triggering, and my result was down counter. Is that true, or I made a mistake? :D
no,it's true..
sir please do a tuitorial on designing of mod n counter and asynchronous counter..
Priyanka Bhadury hi
😂😂😂😂😂😂
Why we need toggling ?
Here for down counter can't we use positive edge triggered clock? It will be far more simple!
I think.....this would be a better option .....Yes we can.
If we use positive edge triggered clock ,race around condition will occur . So it is not preferred.
Clock signal banta kaise hai????