while writing binary equivalent for decimal no. in order the last bit or least significant bit change/toggle every time , while moving towards msb the change/toggle decreases with power of two and same is happening here, Qa is toggling with every input clock pulse so we take it as lsb and Qc is changing at T/2^2 (T/4) so it is acting like msb.
Brilliant !!! as a beginner to digital electronics I find your lessons so clear, very well explained and easy to follow, most importantly I am understanding what is happening in the circuit rather than getting lost, subscription added and I look forward to learning more watching your other videos. Thank you for the great job :-)
I happily postponed studying everyting to the eve of my semester exams because I know I have your videos to save me ❤. You are such a saviour to lakhs of students ❤.
I know this was 4 years ago, but a T flip flop is literally just a JK flip-flop with its inputs tied together. What he used was a T flip flop, but we still just call them JK flip flops for clarity about the underlying logic.
em cảm ơn anh nhiều ạ. Mặc dù em là người Việt Nam nhưng mà nghe cách anh nói rõ ràng bản chất vấn đề, nói đúng trọng tâm và nguyên tắc hoạt động, em mới cảm thấy tại sao người Ấn Độ lại giỏi CNTT đến như vậy, tuyệt vời !!!. Hiện nay em đang là sinh viên Bách Khoa K22 Khoa Khoa Học Và Kĩ Thuật Máy Tính ạ! Thật sự những điều anh giảng dạy quá bổ ích luôn ạ.
You are great. Just great. very great. I understand everything you say on first go only. Do not stop ever. I see your videos at 3x/4x speed to cover many things in short time. Your pace is slow so increasing the speed doesn't impair audio clarity. DO NOT INCREASE THE PACE. Its fine.
I don't know whether I goona get a reply or not but wanna ask a question cant we make the truth table without solving the timing graph? I asked for the competition exam purpose.
Karan Yes, you can. You can see the bits are changing sequentially but if the circuit has some combinational circuit then you have to take care of it in the truth table.
thank you sir for this presentation. but one question in my mind is the logical symbol in the given presentation where is our jk flipflop Qn complement. which part of our Qn complement is connected?
I want to design a counter which can count 0 to 7 except particular 3 states then i can design it but i want to draw a timing digram how to draw what happened my invalid 3 status clock pulses???
You can put logic gates at various outputs and/or inputs in order to design a counter like this. First create the truth table, then write logical equations for each output.
Thank u very much NESO academy ...my concept is 10 0% cleared after watching these videos...plz upld the devideossign of modulo 5 counter...it will be great for me...
Why can't we get an output directly from the clock itself? For example, you made a 3-but counter.. If we consider clock as the 4th bit (LSB), that would increase the states to 16. Am I missing something?
Your lectures help me lot in my exams. Only because of your lectures i understood whole concepts of digital electronics at last time of exam also.You help me lot. So thank you so much sir.....
Sir can you explain and draw the circuit "A digital computer has three registers: A, B and C. Four flip-flops provide the control functions for the computer: S is a flip-flop that is enabled by an external signal to start the system’s operation; L and R are used for sequencing the microoperations; A fourth flip-flop T is set by the computer when the operation is completed. The function of the system is described by the following register transfer statements: S: C ← 0, S ← 0, T ← 0, L ← 1 L: L ← 0, if (A = 0) then (T ←1) else (R ← 1) R: C ← C + B, A ← A - 1, R ← 0, L ← 1 Design a circuit with minimum components to implement the above operations."
A small doubt, I have tried to simulate this circuit in logisim, And I got 111->110->101->...000->111... Result was reverse count, is this the output because I got confused because it's name is Asynchronous UP Counter. Kindly reply
Here, the educator used a negative edge triggered flip flop. The flip flop at the simulator you used must have a positive edge triggering. Draw the clock pulses but with toggling at the positive edge of the clock and you'd see a down count.
Sir one doubt in timing diagram u hav written 011 for 6th falling edge but in table u hav written 110 for 6 count how that's possible if in timing diagram it is already 011
why didn't we use T flip flop instead of jk and just send one input to each flip flops instead of sending the same 1 input to the both terminals of JK flip flop?
engineering colleges should pay him for doing their job
True ❤👌👍
Through paid ad la kan😏
Kerala Technical University should pay first
Exactly!!
@@tom-wz5le Lol
One Indian guy on youtube always save your semester 😁
U r great sir.....
he saved me !!
Me too .. O:)
@@nesoacademy cutie
@@anjalisachan8651 Appropriate :)
Can we do the same by positive edge triggering
how Qa is LSB and Qc is MSB? PLESE EXPLAIN
while writing binary equivalent for decimal no. in order the last bit or least significant bit change/toggle every time , while moving towards msb the change/toggle decreases with power of two and same is happening here, Qa is toggling with every input clock pulse so we take it as lsb and Qc is changing at T/2^2 (T/4) so it is acting like msb.
Friends watch this is 0.75x speed you will understand better 👍👍
I'm watching this at 1.75x speed
Me watching in 2x 💀
jesus, my only regret is not watching your videos sooner. you are really good!! way better than my own teachers lol
thank you so much!!!
Maverick PT Same here
Xctly 💯💯💯
If we apply Q©(complement) as clock instead of Q to the 2nd FF in asynchronous counter does the initial state will be zero? Or it will be 1 according to Q©?
watching this 5 hours before my exam lol
3 hours here lol
24 min lol
@@risabhudgata6620 Lmao 😂🤣🤣😂😂🤣🤣
After exam haha
Lucky u
Brother your channel getting famous day by day, everyone around the world utilizes your channel for studies... A hearty congratulations 👏🙌
dhanneybad neso academy, hamro chiranjibi sir le padhaunu vatheyna dhanna timur le padhayau.
Pidit CSIt 1st sem student 🤣🤣🤣
These Videos are the root Cause of "Make in India"
Can we use t flip flop in place of jk flip flop
Brilliant !!! as a beginner to digital electronics I find your lessons so clear, very well explained and easy to follow, most importantly I am understanding what is happening in the circuit rather than getting lost, subscription added and I look forward to learning more watching your other videos. Thank you for the great job :-)
pls my teacher from uni uses snapshots from your videos in her online classes material💀
please write lecture no. in the heading of your TOPICS...
It Will made Ur leactures more efficient to find them.
Yes it's really easy to identify
It will *make
just go to the playlist
The best videos on Digital Electronics I have seen on TH-cam. Thank you for having spent your time helping us, student, with these videos.
I happily postponed studying everyting to the eve of my semester exams because I know I have your videos to save me ❤. You are such a saviour to lakhs of students ❤.
Plzz upload videos on logic families
Bhai hamare college mein bhi kabi padane aavo
Why didn't you use T flip-flop? Isn't it basically JK flip-flop with common inputs? Thanks for the videos by the way they are great!
I know this was 4 years ago, but a T flip flop is literally just a JK flip-flop with its inputs tied together. What he used was a T flip flop, but we still just call them JK flip flops for clarity about the underlying logic.
em cảm ơn anh nhiều ạ. Mặc dù em là người Việt Nam nhưng mà nghe cách anh nói rõ ràng bản chất vấn đề, nói đúng trọng tâm và nguyên tắc hoạt động, em mới cảm thấy tại sao người Ấn Độ lại giỏi CNTT đến như vậy, tuyệt vời !!!. Hiện nay em đang là sinh viên Bách Khoa K22 Khoa Khoa Học Và Kĩ Thuật Máy Tính ạ! Thật sự những điều anh giảng dạy quá bổ ích luôn ạ.
Hehe sinh chào tiền bối, em cũng đang lú môn hệ thống số :)))
@@Hatsumi_candy3 kkk, thi tốt nha em
why have you taken output a as the least significant whereas output c as the msb ?plz explain
You've accidentally written Qc at the beginning of the table in place of Qa!!
Yes
Thanx bro👏 u made it easy for understanding. Ensure all ur videos are safe for the future too have back up in servers too.
sir,your lectures are great
i just want to ask you one thing why are you not using preset and clear
Sir ,if it is not specified the type of counter ( synchronous/asynchronous) in question ,
then what should I need to do
Actually sir i have a doubt that is when i used this diagram in logism to understand how it works. It actually starts from 7 and goes to 0
Down counter
Actually it is diagram of down counter
Thank you so much sir. You helped me a lot in this subject! May God bless.
You are great. Just great. very great. I understand everything you say on first go only. Do not stop ever. I see your videos at 3x/4x speed to cover many things in short time. Your pace is slow so increasing the speed doesn't impair audio clarity. DO NOT INCREASE THE PACE. Its fine.
excellent work! understanding each n Every part now. Thnk you so much!
I don't know whether I goona get a reply or not but wanna ask a question cant we make the truth table without solving the timing graph? I asked for the competition exam purpose.
Karan Yes, you can. You can see the bits are changing sequentially but if the circuit has some combinational circuit then you have to take care of it in the truth table.
In synchronous counter, what is the purpose of finding the output of 1st flip flop??
Plz answer
thank you sir for this presentation.
but one question in my mind is the logical symbol in the given presentation where is our jk flipflop Qn complement.
which part of our Qn complement is connected?
these presentations were so very useful... :)
Engineering universities like NUST which is no 1 University of Pakistan should pay him for this excellent explanation.
hahah nice joke but i don't pakistan can pay to anyone execpt their army
I want to design a counter which can count 0 to 7 except particular 3 states then i can design it but i want to draw a timing digram how to draw what happened my invalid 3 status clock pulses???
You can put logic gates at various outputs and/or inputs in order to design a counter like this. First create the truth table, then write logical equations for each output.
Thank u very much NESO academy ...my concept is 10 0% cleared after watching these videos...plz upld the devideossign of modulo 5 counter...it will be great for me...
Excellent Explanation..👏👏
Sir.. in the block diagram you did not use any reset there .. then how the circuit will be change to initial state in the middle of operation
If we are feeding the same input to both J and K of JK Flip Flop, why not to use T Flip Flop?
sir....ur teaching is really soo awesome...but a kind request that please give your lecture number at the topic head...
Why can't we get an output directly from the clock itself? For example, you made a 3-but counter.. If we consider clock as the 4th bit (LSB), that would increase the states to 16. Am I missing something?
Why we don't simply use the Toggle flip flop?
Which type of counter are they using jk t which one?
great helped so much smart guy. thank you so much.
That was a great lecture. Thank you again! =D
and I regret that I'm watching these videos a day b4 my exams...
Same 😅
You must be thankful as you are watching it the day before and not the day after of the Exam :)
Is it possible to construct a arbitrary sequence counter by using asynchronous counter
Your lectures help me lot in my exams. Only because of your lectures i understood whole concepts of digital electronics at last time of exam also.You help me lot. So thank you so much sir.....
Can't we use t ff. directly
Then it becomes more simpler.
Suraj kumar Mondal yeah we can
Sir can you explain and draw the circuit
"A digital computer has three registers: A, B and C. Four flip-flops provide the control functions for the computer: S is a
flip-flop that is enabled by an external signal to start the
system’s operation; L and R are used for sequencing the microoperations; A fourth flip-flop T is set by the computer when
the operation is completed. The function of the system is described by the following register transfer statements:
S: C ← 0, S ← 0, T ← 0, L ← 1
L: L ← 0, if (A = 0) then (T ←1) else (R ← 1)
R: C ← C + B, A ← A - 1, R ← 0, L ← 1
Design a circuit with minimum components to implement the above operations."
I have watched almost all of ur lectures on digital electronics they were very helpful...u did a great job sir..
The best presentation for digital electronics
Thanks a lot
Your lecture is so good and understandable...thanks...!!
Sir can you please tell me how to design 3 to 12 bit asynchronous counter?
Thankyou for your contribution towards our studies
Just Magnificent. Videos are concise and full of important points on digital logic design.
Qa, Qb and Qc are swapped in the table by mistake. Anyway, great explanation
I love this guy already!
thanks neso for this wondeful lectures
excellent work !!where can i find the lectures ??
Thank you so much sir, you are making soo many learn the subject
I respect you! Thanks a load!
Loved all the videos
sir can u please answer me that why Qa, Qb, Qc initially are zero ??? cant we make them high ?? or what senario can make it high at the beginning ?
A small doubt, I have tried to simulate this circuit in logisim, And I got 111->110->101->...000->111... Result was reverse count, is this the output because I got confused because it's name is Asynchronous UP Counter. Kindly reply
Here, the educator used a negative edge triggered flip flop. The flip flop at the simulator you used must have a positive edge triggering. Draw the clock pulses but with toggling at the positive edge of the clock and you'd see a down count.
clean and clare lecturing
Sir you are using JK flip flop? Even race condition occur in jk.
What if we have to count from 3-7?
If the input to J and K are always the same, why not use T flipflop, wouldn't that be easier?
very good explaination by you sir ,Thank you so much
ur videos are very very helpful.. spcly just before the exam this type of videos are very much required.. thank you for this help...
why triggered jk fllip flop is used?
To avoid race around condition
Sir...why toggling is required in counters?
Great teaching 👏Thank you sir ❤️
what is the reason of using negative edge triggering
There is no specific reason, we can also use +ve trigger. Wave diagram will change accordingly.
sir ur making subject look so easy thanks
what if the clock is positive triggered .? Will it still work?? PLS ANSWER !
You have to use Q' as clk pulse for the successive flip-flops
If you use same Q as input then you will get down counter
Bravo.....fasinating
WOOHHOOOOOO
आपका बहुत-बहुत धन्यवाद। मुझे पाठ अच्छी तरह समझ आया, आपका धन्यवाद। इराक से नमस्कार
Explanation was Excellent
Sir one doubt in timing diagram u hav written 011 for 6th falling edge but in table u hav written 110 for 6 count how that's possible if in timing diagram it is already 011
Thank you Sir ❤️🔥
What 127 dislikes the student's couldnot be the engineering students because they dont understand the concept which is explaind simple
Why we use negative edge triggering, I couldn't understand, pls tell me😢
Qc least significant bit hoga na
why didn't we use T flip flop instead of jk and just send one input to each flip flops instead of sending the same 1 input to the both terminals of JK flip flop?
What if we use rising edge in counter? Would there be any problem?
if we use rising edge than it would behave as a Down counter
SIR OPEN YOUR VIDEO RIGHT NOW!!!!!!! FAST BEFORE I CALL YOUR PARENTS!!!!!!!!
Guys, what would happen if we plug QA' to the clock instead of QA. Would QB be positive edge triggered?
How about 3 bit flip flop d and asynchrous sir
Help pls :)
Also, can you make a counter count from 1 to 3 (i.e. odd number of states) ? How would that be implemented with FFs ?
Why negative edge triggering? And why don’t use T flip flop instead ?
I ws struggling to umderstand this .. thank u soo much sir.. u wll b the reasn if i pass my test tomorw.. tq
Sir, why we use flip flops operating in falling edges, mostly?
The right Qc will be QA. (Not correcting , Just helping)
sir plz upload asynchronous sequential circuit,
in detail
watching this during quiz..
IS IT 3 BIT ASYNCHRONOUS UP COUNTER WITH NEGATIVE EDGE TRIGGERING??