amazingly explained....i have been able to solve almost all gate previous year questions by going through almost 200 lecture made by you..i was lacking in counters so come to watch your lecture again..now concept is perfectly cleared again...If possible please make such courses for other cse subjects....
You are the best teacher on this subject that I found on the TH-cam. Very clear and easy to understand. Thank you so much.Take my love sir.From Bangladesh 🇧🇩
Your videos are the best for students, instead of wasting time on books, if anyone watches all these videos he/she can fully grasp the concept . Thanks for all your vidoes
sir your teaching videos are like RED BULL DRINK to who(to engineering students ) is walking in a desert(engineering collages without good DD teacher)... good job sir .A VERY SPECIAL THANKS FROM NIT MANIPUR STUDENT.
hello sir,it had been very interesting to watch your lecture , the way you explained all sections of digital techniques .i have gone through your videos and i have understood all concepts which you presented.thank you for being guideline .
First of all thanks for creating this playlist. Like its been 9 years since its uploaded and till today it is helping so much students. I am preparing from your channel solely for my Digital Logic Design Exam. But I am confused a bit about the MOD condition. We used a NAND gate that generates output of 0 when the MOD = 0 occurs. But when the output of NAND goes in JK-FF it is inverted as seen in the diagram that it have a bubble. So instead of NAND we should use AND gate so we generate output of 1 and when it is sent to flip flop at clear it become zero and flip flop is cleared.
brother first of all i want to thank you a lot for such a great and deep explanation of this topic. But i'm a little bit confused that when we were making a mod6 counter than why we reset our ckt on 6th clock cycle cause if 6th cycle applies then our ckt will definitely count till decimal 6(which we don't want) and then it will reset.
Repping Machakos University, never made an appearance to my Digital Electronics II class and I have a CAT tomorrow. Hope this helps. If it doesn't, I deserve it.
I disagree, i think we should trigger CLEAR when '5' appears , becoz Qc ,Qb, Qa, already show 101 before triggering CLR, , after '5' they trigger CLR and display '0'. Plz convince me how '6' is "Not displayed" when Qc ,Qb, Qa, = 110 after then they trigger CLR, , (in your ckt 12:30 onwards , i think '0' appears at 7th clk edge and 110 = 6 appears at 6th clk edge )
6 will be the output(QcQbQa) for the time equal to the propagation delay of the combinational circuit. As soon as the combinational circuit detects 6(110) as input, the clear is set to 0. This clear will ASYNCHRONOUSLY (ie . clock independently without encountering the negative edge)update the outputs as 000(QcQbQa) and the counter will function as normal for next states. *Clear and Preset are asynchronous overriding inputs. .They don't depend on the clock edge.
sir your greatest teacher I ever know. Pleeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeease sir ,upload classes for Artificial Intelligence, Neural Network, Graphics in computer science.
Important: The nand gate should be designed on 101 ( at 5 as output) as we dont want 6 as output so it must be reset befor 6 is arrived i,e. at 5 as output we clear the flipflops. rest everything is correct 👍
@@SNEHAKANDPAL-ev3np You clear your outputs when it reaches 110 (representing a decimal value of 6). It will be your output only for a short period of time. For example, if you are designing a counter up to 13, you want to reset it on 14. Because if you reset it on 13, you will lose that data.
"I hope you have watched my presentantion" Me:"Fine ill look it up." Video i look up:"I hope you have watched my presentation on...." Me:"Okay,ill look that up" Next Video:"I hope you have watched my presentati-" Me:"..." Your videos are awesome tho,reminding us to check the presentantion helps to understand everything without missing something important and to put things in a correct order.
In this example, the requirement for the counter is to count up to 5 (101), however, the combinational circuit for the clear input allows the counter to count up to 6 (110). I'm thinking that the combinational circuit for the clear input should be (Q_A Q_B' Q_C)'. That is once the counter reaches 101, the counter should start counting from 000. Please let me know if i missed something. Thnaks!
Hii sir ... I am from Hyderabad... I have a doubt please clarify.. At 10:39 you connected logic 1 to preset so that no changes will happen. But at preset you have given a bubble then preset takes logic 0... In that case Then all Qa,Qb,Qc values will become 1,1,1 thent it is completely contradict to our question.
Once the count reaches 111 Make a NAND gate that gives zero only when all of outputs are one. Use it to reset the first , preset the second and reset the third that way, it will be 2.
Great! If I want to build a counter that change states from 0 to 2 to 4 to 6 and to 8 in decimal, how can i do this? Should i build a ecitation table or something like that ?
You use the Mode select signal when you have an up/down counter, to change between the modes. Here, he is only describing an up ripple counter. Ripple refers to the asynchronous clocking of the flip flops.
I think we should design combinational circuit at 5(101) not at 6(110) Becoz, if we design combinational circuit at 6(110), Then we also must get 6 at the output...but we need to skip it as they asked for mod-6 counter not for mod-7 counter Pls correct me if iam wrong
sir, questn, does the NAND gate logic work for all counters that count to a specific value, in this case we caount to dec5 and after that it restarts from 0 and the NAND gate helps did that, what if we want to count to 7 and reset after that, will the NAND logic still work in that case?
dear sir please explain, if we dont have negative logic for PST & CLR (so the PST=1 -> Q=1 & CLR =1 -> Q=0) inputs, are we supposed to use nor gate instead of nand fore reset condition?
You are the best teacher on this subject that I found on THE INTERNET. Very clear and easy to understand. Thank you.
+Trai I agree. Nesa Academy is awesome!
U guys juz over portraying abt the author...many channels have better explanation than this
@@kavinashokan5692 but I didn't find anyone better than him..
@@ipankaj_patel
He is good....u can use his videos to clear the questions asked in Qualcomm as I did...
Absolutely right brother...
amazingly explained....i have been able to solve almost all gate previous year questions by going through almost 200 lecture made by you..i was lacking in counters so come to watch your lecture again..now concept is perfectly cleared again...If possible please make such courses for other cse subjects....
My professor is playing these videos in class directly , please rise copyright issue on him 😵😂
omg, which good college allowed it?
Many professors are folowing him now
@@Idiot_Indians following is different from directly downloading and playing/uploading videos ryt?
Damn same here😂
Damnnnn😂
now these words are really small for such quality lectures that u provides us for free, but again thank u sir...thank u for being here
You are enough for me to complete this course successfully...
loga rathinam Haven't your friends ever called you "logarithm?"
@@ir2001 hahahaha lol
I was searching a good video on counter from last 1 week and today I got the Best one thnx a lot sir 🙂
Thanks a lot neso academy. Because of you I got good marks in digital logic and design. Thank you!!!🎉
You are the best teacher on this subject that I found on the TH-cam. Very clear and easy to understand. Thank you so much.Take my love sir.From Bangladesh 🇧🇩
Your videos are the best for students, instead of wasting time on books, if anyone watches all these videos he/she can fully grasp the concept . Thanks for all your vidoes
Sahi kaha
Thank you so much❤, I have exam to write today and you made me understand what my lectural could not explain well..
sir your teaching videos are like RED BULL DRINK to who(to engineering students ) is walking in a desert(engineering collages without good DD teacher)... good job sir .A VERY SPECIAL THANKS FROM NIT MANIPUR STUDENT.
Almost like classroom teaching.. very nice... Appreciate all the effort :)
These are best lectures on digital electronics even after 8 years !!! ✨🫡 Unbeatable
i just can't believe that its 7years old video and still one of the best!!!
Completed digital in sem successfully by watching your video♥️♥️♥️
These videos are very useful to me. U'r way of teaching style is excellent. Very thankful sir......
Tomorrow it's my sem exam and now i am watching all the things😂
1hr before here😎😎
Yeah I'm also😂
hello sir,it had been very interesting to watch your lecture , the way you explained all sections of digital techniques .i have gone through your videos and i have understood all concepts which you presented.thank you for being guideline .
I couldn't get to understand counters up till now. Thank you very much. I keep studying from you videos.
one request i want to do is, post videos on VHDL and memories as soon as possible.
Amazing 😍. Indeed, you have explicated everything sir. May God bless you and increase the knowledge abundantly.
As per waveforms clock is sampling data just before the negedge, so it should read 5 (101) and then do clear instead of 6.
First of all thanks for creating this playlist. Like its been 9 years since its uploaded and till today it is helping so much students. I am preparing from your channel solely for my Digital Logic Design Exam.
But I am confused a bit about the MOD condition. We used a NAND gate that generates output of 0 when the MOD = 0 occurs. But when the output of NAND goes in JK-FF it is inverted as seen in the diagram that it have a bubble. So instead of NAND we should use AND gate so we generate output of 1 and when it is sent to flip flop at clear it become zero and flip flop is cleared.
jitni tareef karo kaam hai, best lectures on dl ever made
i only found you at the seconnd half of my semester and i regret bnot finding you for ,my mid terms so badddddddd you are so good
very clear and helpful. A big thanks from RV college of engineering student.
6:20 is all I needed.
Thanks!
Thank you very much .. Clear and precise explanation better than any book
Thank you very much , the best in digital electronics
Excellent teaching skills and good stuff to spend our valuable time
Your videos helped me a lot... Thankyou
found this channel just in time for my exam, you are a life saver
Sir in the description please upload the contents of the board as pdf so that we can use them as notes.
The way u taught is really commendable!!!!!!!!!!!!!!!!!!!!!!!!!
You guys are doing a great job.
You are best Teacher and very helpful
Great explanations ever
Thanks a lot sir for ur videos🙏🙏🙏🙏🙏
fabulous brother, you are great teacher..........................................
brother first of all i want to thank you a lot for such a great and deep explanation of this topic. But i'm a little bit confused that when we were making a mod6 counter than why we reset our ckt on 6th clock cycle cause if 6th cycle applies then our ckt will definitely count till decimal 6(which we don't want) and then it will reset.
Clock starts counting from 0, so the 6th clock will count 5 and the 7th will again start from 0 (probably)
GOD give me gift through you. so thankyou so much sir.
please upload remaining video as soon as possiable .
i highly obliged for this
Repping Machakos University, never made an appearance to my Digital Electronics II class and I have a CAT tomorrow. Hope this helps. If it doesn't, I deserve it.
(9:56) when clear is 0 output is 0. But this is low active clear so shouldn't 1 be given to clear instead of 0???
9:23 we can use a 2 ip nand gate with Qb and Qc as inputs, right??
you explain things better thant my university professor. thinks for you nice job
Another Approach towards such Q's
I want a function which gives o/p as 0 for value >= 6. Other wise 1 for value
I disagree, i think we should trigger CLEAR when '5' appears , becoz Qc ,Qb, Qa, already show 101 before triggering CLR, , after '5' they trigger CLR and display '0'.
Plz convince me how '6' is "Not displayed" when Qc ,Qb, Qa, = 110 after then they trigger CLR, ,
(in your ckt 12:30 onwards , i think '0' appears at 7th clk edge and 110 = 6 appears at 6th clk edge )
if we do what u have said...5th count state will be unstable...so when 6 came it is cleared..and 000 will come
6 will be the output(QcQbQa) for the time equal to the propagation delay of the combinational circuit. As soon as the combinational circuit detects 6(110) as input, the clear is set to 0. This clear will ASYNCHRONOUSLY (ie . clock independently without encountering the negative edge)update the outputs as 000(QcQbQa) and the counter will function as normal for next states. *Clear and Preset are asynchronous overriding inputs. .They don't depend on the clock edge.
@@sarthaksg thx
I too think that when 101 is countered immideately clear should be triggered
Sir The way you teach is awesome. thank you
Very Clear Explanation
amazing!
Worth Watching ads! :)
8:58, but from where are you getting those Qa, Qb and Qc? shouldn't it be connected to flip flop outputs?
Thank you Neso
Thank you very much . I should send the link to my professeur
honestly....Ur teaching was fabulous😃😊
sir your greatest teacher I ever know.
Pleeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeease sir ,upload classes for Artificial Intelligence, Neural Network, Graphics in computer science.
Important:
The nand gate should be designed on 101 ( at 5 as output) as we dont want 6 as output so it must be reset befor 6 is arrived i,e. at 5 as output we clear the flipflops. rest everything is correct 👍
Then 5 won't show up in output, right?
@@Randsome1but how would you get Qa,Qb,Qc corresponding to 101 for generating clear if the output corresponding to them isn't displayed?
@@SNEHAKANDPAL-ev3np You clear your outputs when it reaches 110 (representing a decimal value of 6). It will be your output only for a short period of time.
For example, if you are designing a counter up to 13, you want to reset it on 14. Because if you reset it on 13, you will lose that data.
@@isuckatthisgame Yes I got it. Thank you
"I hope you have watched my presentantion"
Me:"Fine ill look it up."
Video i look up:"I hope you have watched my presentation on...."
Me:"Okay,ill look that up"
Next Video:"I hope you have watched my presentati-"
Me:"..."
Your videos are awesome tho,reminding us to check the presentantion helps to understand everything without missing something important and to put things in a correct order.
Saying Thank U is not enough
Fabulous.....
Can I use 2 input nand gate and set its input as Qc and Qb...??
well explained sir..all my doubts are cleared after watching this video.
In this example, the requirement for the counter is to count up to 5 (101), however, the combinational circuit for the clear input allows the counter to count up to 6 (110). I'm thinking that the combinational circuit for the clear input should be (Q_A Q_B' Q_C)'. That is once the counter reaches 101, the counter should start counting from 000. Please let me know if i missed something. Thnaks!
***** Oh, I see. Thank you for clarifying this to me.
@@hassanalshehri6855 bro you're right 👍♥️
Thanks very much💯💯💯
Hii sir ...
I am from Hyderabad...
I have a doubt please clarify..
At 10:39 you connected logic 1 to preset so that no changes will happen.
But at preset you have given a bubble then preset takes logic 0...
In that case
Then all Qa,Qb,Qc values will become 1,1,1 thent it is completely contradict to our question.
Here bubble means that it works as active low signal means whenever 0 is given as input it will set Qa...Qc to 1. ☺️
bubble represents that the input should be active low and doesnot changes the input
ive watched basically all ur sequential circuit vids and they are mint
What if I'd like to perform this way of counting: 0--> 3-->6-->2-->3-->5-->6?
Will it be possible using the counting way u've shown us?
thanku sir!
your lectures have helped me a lot😊
What if we have to start our count from a particular value say 2 (010)?
Once the count reaches 111
Make a NAND gate that gives zero only when all of outputs are one.
Use it to reset the first , preset the second and reset the third that way, it will be 2.
Thank you so much. You ARE GREAT!
Great! If I want to build a counter that change states from 0 to 2 to 4 to 6 and to 8 in decimal, how can i do this? Should i build a ecitation table or something like that ?
Thank you so much for everything sir. We want gate EEE of all subjects sir please kindly do this for poor students sir 🥺🥺
can we use a decoder instead of the NAND gate to restart our counting
So, the same clearing and presetting idea can be used for counting down to a particular value also?
assalam o alakum i just want to say you are the best teacher of this subject
Great videos! Just have a doubt that if this is a ripple counter why aren't we using Mode control input (MCI) as you taught in previous videos?
Because this is a up counter.
You use the Mode select signal when you have an up/down counter, to change between the modes. Here, he is only describing an up ripple counter. Ripple refers to the asynchronous clocking of the flip flops.
Simple n clear explanation.. inshallah I will score sooprgrade
fabulous!! appreciate ur effort...
In the state diagram of counters with unused states, the unused states can be added to any valid state, or there must be some reason to add it?
I think we should design combinational circuit at 5(101) not at 6(110)
Becoz, if we design combinational circuit at 6(110),
Then we also must get 6 at the output...but we need to skip it as they asked for mod-6 counter not for mod-7 counter
Pls correct me if iam wrong
really it was helpful for me during exam period.
my prof should watch these lectures
Excellent teaching .
very good lectures regards NIT KKR
Very instructive. Thank you !
im not good in english but i understand you very well. niiice
sir, questn, does the NAND gate logic work for all counters that count to a specific value, in this case we caount to dec5 and after that it restarts from 0 and the NAND gate helps did that, what if we want to count to 7 and reset after that, will the NAND logic still work in that case?
Thanks a lot bro🙏 ur the best
Very good explanation
keep posting such videos..!!!!
very helpful...!!!!
sir you are fabulous
Thanks a lot sir....
Sir, can we just solve the K-Map for MOD 6 counter?? Then combinational logic will become NAND of Qb and Qc..
If I want to use down counter what type of difference will be there?
The sexual tension betweern the NAND gate and me when he pronounced SIX
Please explain the generation of spikes or glitch
Concept cleared👍🏻 tysm !
@nyone please answer quickly!
Do we have to use both the preset and clear inputs simultaneously or we can use only one of them ?
Sir u r like a god for us...
Love u and gbu sir
will there be 110 for brief amount of time during which decoding logic will clear
Great! Now I got it. Thank you so much.
dear sir please explain, if we dont have negative logic for PST & CLR (so the PST=1 -> Q=1 & CLR =1 -> Q=0) inputs, are we supposed to use nor gate instead of nand fore reset condition?
thanks sir,love from VIT VELLORE , TEACHER dhanabal
really best digital electronics lecture for BTECH students in whole youtube
saved my semester