Can't appreciate your amazing explanation enough! Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!
As clear is active low signal so it will work when clr=1 because when clr=1 then input to ff from clr =0 and output=0 So according to this concept the output of the nand gate should =1 to active the clr input but you are doing opposite to this? Please clear my doubt Am I wrong or you taught wrong?
Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.
I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.
Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values
Good morning sir. You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs. Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately? Am I missing something? Thank you for the lectures.
i think --------------- for PRESET you have to input (0) for PRESET and it will change to (1) because the NOT gate on the flip flop because i do not wont PRESET effect on the result (Q) -------------------------------------------------------------------------------------------------------------------------------------------------------- for CLEAR you have to use AND gate to get (1) and it will change to (0) because the NOT gate on the flip flop because i wont to reset the flip flop (0000) --------------------------------------------------------------------------------------------------------------------------------------------------------- THANKS
sir, if we use +ve edge triggered clock then what about race around condition ?? you taught that to overcome race around condition we use -ve edge triggering .
Good morning sir. You have explained that we have to clear the counter after 1001 (9). So upon the arrival of 1010 we clear the counter. My question is when Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since Qd Qc Qb Qa are our outputs. Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately? Am I missing something? Thank you for the lectures.
sir pls i have doubt about it,,is it ic 7490 ripple counter,,because when I reffer ic 7490 ripple counter internal diagram it's seems like little different from u mentioned in video pls suggest fast i have exams 2 days after
he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different
Sir, since we do not want 1010 to appear as the output, shouldnt we feed 1001 as the input of the NAND gate? If we reset after seeing 1010 output, dont we somehow count from 0000 to 1010?
Yes we will in fact see for a short period of time 1010 as the output. To solve this problem we can connect the Clock-Enable input of the 4th Flip Flop with the output Qa of the first flip flop. Then we need to connect the J input of the 4th Flip Flop to an AND gate of Qb and Qc. As a result the Qd changes state only when Qa drops from 1 to 0 and Qb=Qc=1and resets to 0 when Qa drops from 1 to 0 every other time (J=0,K=1) .
a synchronous decade counter (a synchronous MOD -10 counter ) with timing diagram & 4 bit asynchronous counter(4 bit ripple counter) please send me link
I am 62 years old and I follow digital design as a hobby.I want make a JK FF counter that gives the sequence 10,22, 5.4.3. I have seen a lot of your interesting videos but I cannot figure out how to do it. Can you give me a hand ? Theodore from Greece.
It is indeed a fabulous lecture ..which content clear ...but only one correction at the en d..for the two input nand gate you must take qc and qa as 1 nand 1 is 0 but in the lecture the two inputs are qd and qb whose nand is 1 and clr would be 1 ..And sorry for poiniting out such a silly mistake for a great lecture . And shouldnt we stop at 1001 and not at 1010 , because 1010 might also be printed , becoz we are print qd,qc , qb, qa? Correct me if I am wrong
sir if I make a flip flop then how would I know that it is a positive edge triggered or negative edge triggered flip flop or level triggered. I know that what is positive /negative / level triggered but how do I implement this triggering?
BCD counter is the part of synchronous counter by m.morris mano(digital logic and computer design) but you say it is the part of asynchronous counter. so i want to know which is real???????? plzzz tell
+Praina Malik arey sir in this presentation explained bcd ripple counter , which is asynchronous.But there is also synchronous bcd counter.I too follow m.morris book
When to take output in counter with respect to clock pulse in negative edge triggered flip flop?? 1)At the start of clock pulse or 2)At the end of clock pulse
the outputs have to be 1010 for not gate to reset the contour so since the outputs are 1010 does that not mean we are already showing number 10 on the display before resting??? please help Im really confused about this. Thank you all.
in 2:09 when you are discussing positive edge trigger you are telling about the clock but not about the output clear from where you are taking the output when positive edge triggring
Making reset as an NAND of Qb and Qd would not show 12 and 13 ???And hence disturbing our BCD counter???bcz they are 1100 and 1101 respectively and NAND of their Qb and Qd is 1???
You really work hard, I'm worried because I clear concept here but what about semester exam we've to write more and how will we write because we don't have content?
It's not that we can just pass our semester exams with ur lectures ..... it's all GATE level content that u r teaching for free👏👏👏 Hat's off to u sir
its my exam today and at 3:00 am I am listening to your lecture ......... thnks sir
And me at 5:00 am
M1 at 237
Can't appreciate your amazing explanation enough!
Just a simple correction- I think (at 7:55) the signs of the NOT gates should be mirrored, for Qc and Qa. Correct me if m wrong here...!
Yup that's correct!
@@shubhranginidas6818 ohh wow u r clearing his doubt after 1 year
As clear is active low signal so it will work when clr=1 because when clr=1 then input to ff from clr =0 and output=0
So according to this concept the output of the nand gate should =1 to active the clr input but you are doing opposite to this?
Please clear my doubt
Am I wrong or you taught wrong?
Hello, if I have a asynchronous/ripple D flip-flop counter with a count sequence of 10, 9, 8, 7, 6, 5, 4, 3 and repeat but with provition for a logic 0 output on 8 and a logic output on 6, how exactly would I go about with this kind of a question. I understand that I will use the positive egde triggered and Q would be the clock. I would the connect the NAND gate with input 3 to clear to ensure that it will repeat the sequence but what of the provitions and would the sequence start at 15 and go down or would I also need to connect a NAND gate to PRE so it starts at 10. Any help would be much appreciated.
Where r we taking the output in cases mentioned in the starting of the video
Output is same Qa Qb Qc Qd
But there due to 1010 -10
1 should convert to 0 so nand gate is used for Qd Qb in this case
Dacade is for 0-9 decimals
Heroes fight for their people from behind their masks.
Neso Academy fights for students from behind an electronic board.
not a suitable dialogue
good try 🤣
😁 benki🔥
i learnd more stuff in a 9min video than a 90min lecture
rather 4.5 min at 2x speed
I feel you..
same man this is excuse i gave to my family when they ask why you arent going university
@@owaiswasim8911 🤣
I wish this guy could cover all of my undergrad degree because his videos are much better than 90 min lectures
you drew the NOT gate symbol in the wrong direction
sir its only because of ur videos i cleared my exam..thnx a lot..keep it up
hopefully +1
I just clapped with joy at the end. 👏👏 You cannot imagine how fast I understood everything after watching this video...I just enlightened my class knowledge 100 times! The best Electronic course tutorials are here my fellow engineers.
U JUST SAVED MY LIFE THIS SEMESTER
Wow! With this knowledge, the possibilities are endless. Imagine, instead of clearing each flip flop's state to zero, you use the same NAND gate but connect it to PST and CLR on each FF in a different way. You could manipulate this to use counters to skip to different values
Now I'm confident about my interns. Thank you
Good morning sir.
You have explained that we have to clear the counter after 1001 (9).
So upon the arrival of 1010 we clear the counter.
My question is when
Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since
Qd Qc Qb Qa are our outputs.
Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately?
Am I missing something?
Thank you for the lectures.
same question
They are asynchronous so output will not wait for next trigger and went off
tommorow is my dld exam.hoping to get good marks because of your videos.
sir ur lectures are truly worth it gave me great understanding .
sir i also want a lecture on how to design a counter which have only the even states.
i think
---------------
for PRESET
you have to input (0) for PRESET and it will change to (1) because the NOT gate on the flip flop
because i do not wont PRESET effect on the result (Q)
--------------------------------------------------------------------------------------------------------------------------------------------------------
for CLEAR
you have to use AND gate to get (1) and it will change to (0) because the NOT gate on the flip flop
because i wont to reset the flip flop (0000)
---------------------------------------------------------------------------------------------------------------------------------------------------------
THANKS
Thank you so much for all the DE videos...they helped me score really good in my finals...
Woww my favorite channel
Thank you so much❤
thank you so much sir these videos are so much helpful
sir, if we use +ve edge triggered clock then what about race around condition ??
you taught that to overcome race around condition we use -ve edge triggering .
+sumit shekhar LPC
It takes place in level triggering
To overcome it we use 3 methods
1)(T/2)>FF propagation delay
2) edge triggering and
3) master slave JK flip flop
Good morning sir.
You have explained that we have to clear the counter after 1001 (9).
So upon the arrival of 1010 we clear the counter.
My question is when
Qd Qc Qb Qa (1010) has arrived, we have that count (which was to be eliminated ), since
Qd Qc Qb Qa are our outputs.
Is that count momentary bef the FFs are cleared? Or the action of the clear is so fast that the FFs are cleared immediately?
Am I missing something?
Thank you for the lectures.
Same doubt.. did u get the ans?if so type it pls
earlier in down counter video, you used negative edge triggered and Q as clock, you have not mentioned that in this lecture?
A small Mistake is that when using CLEAR (Qd,Qc,Qb,Qa)=0 then when you are using NAND gate inputs should not be Qd and Qb instead Qd NOT And Qb NOt.
sir pls i have doubt about it,,is it ic 7490 ripple counter,,because when I reffer ic 7490 ripple counter internal diagram it's seems like little different from u mentioned in video pls suggest fast i have exams 2 days after
he give 2 clock inputs a and b ,,output of 1st flip flop not given to second as clock,,he gives 2nd input to second flip flop and then ckt is similar,,an logic used that is also different
I was struggling for 3 hours with a problem. Thank God I watched this video!
One minute into the video and ta-da ! Problem solved. :)
bache ki jaan bachali apne bauji ,dhanyawad :))
sir can u upload bcd counter with parallel load. . ?
In my book it says to draw kmap for output states then draw circuit for clear input. Here we are taking just the first invalid state
Great
for positive edge triggered FF the race around condition will appear.How could it be used as counter?could you please explain.
Sir, since we do not want 1010 to appear as the output, shouldnt we feed 1001 as the input of the NAND gate? If we reset after seeing 1010 output, dont we somehow count from 0000 to 1010?
Yes we will in fact see for a short period of time 1010 as the output. To solve this problem we can connect the Clock-Enable input of the 4th Flip Flop with the output Qa of the first flip flop. Then we need to connect the J input of the 4th Flip Flop to an AND gate of Qb and Qc. As a result the Qd changes state only when Qa drops from 1 to 0 and Qb=Qc=1and resets to 0 when Qa drops from 1 to 0 every other time (J=0,K=1) .
a synchronous decade counter (a synchronous MOD -10 counter ) with timing diagram & 4 bit asynchronous counter(4 bit ripple counter) please send me link
Thank you sir, you have exceptional teaching skills!
I am 62 years old and I follow digital design as a hobby.I want make a JK FF counter that gives the sequence 10,22, 5.4.3. I have seen a lot of your interesting videos but I cannot figure out how to do it. Can you give me a hand ? Theodore from Greece.
It is indeed a fabulous lecture ..which content clear ...but only one correction at the en d..for the two input nand gate you must take qc and qa as 1 nand 1 is 0 but in the lecture the two inputs are qd and qb whose nand is 1 and clr would be 1 ..And sorry for poiniting out such a silly mistake for a great lecture . And shouldnt we stop at 1001 and not at 1010 , because 1010 might also be printed , becoz we are print qd,qc , qb, qa?
Correct me if I am wrong
3:52 maximum point is 2^n-1formula 10-1 = 9 didn't understood that
Why have we used PST here , can't we implement BCD without PST
If preset is 1 then output is going to be 0 and reset all time then why we connect preset to 1🤔🤔
The besttt teacher ever
thanks this qs came in exam but with a twist qs was
design a ripple decade counter using jk ff without clr and preset signals
i don't have any words to thank u
Thank You So much Sir...it's just because of you i am able to understand Digital Logic circuits course which is in my present semester.
Thanks sir .Watching from Nepal
What type of counter do we get if flip flops include both negative and positive triggered flip flops
Sir does FF know That we have come to state 10 as we are not giving output of FF to NAND I/p to get know that we are at 10
if we place positive edge trigger how can it be JK flipflop??
Someone - Hei. What is your campus?
My mind - Neso academy
all your lectures are superb sir.
thanks a lot!!
please clear more why you use clear and preset if bpossible please give the answer today
Aapke video dekhen aur phir kitab se padhen,
😂😂😂😂😂😂😂😂😂
Bro , you should ,after all this great jobb, applet to patch board.. Please
thanks, now i am understanding the working of computer
Why we are restricting to 10 when we are having chance up to count 16.
Why all ff circuites are in negative edge triggering? Any reason
Is there any difference between MOD 10 asynchronous counter and decade counter
Both are same
Here we will take Q as o/p for all config dont deal with Qbar for o/p
What do you mean by (MN) wheather M*N or simply MN at the time of cascading the counters??
Apka jo v conversation write hota h niche jiske wajah se content nhi dikhta h prblm hota h next video aap ye chiz na karen
Will u send Vhdl code for decade counter
Instead of using a nand gate and a not gate why don't you just use an and gate?
In our college they are using and gate ....pls reply
how to make a counter which start from any no. that we want
for ex. i want a counter which counts from " 3, 4, ...,8".
plz explain.......
can someone tell me what is the program he use to write his notes?
i think we need to clear at 1001 condition am i right??
it is very easy method for all ece students
sir is 10 wali nand gate wali ckt kha se connect hogi ye clear ni ho rha pls tell me jo clear kr ri h
Is it possible to make this with Toggle flip flop?
please give a proper explanation on this question
How to draw 6 mod counter using d filli flop
sir if I make a flip flop then how would I know that it is a positive edge triggered or negative edge triggered flip flop or level triggered. I know that what is positive /negative / level triggered but how do I implement this triggering?
Can anyone help me how to sketch a 4-bit asynchronous decade counter and decode the numbers 4(active high) and 6(active low) pls🙏
Can anyone tell me the difference between designing a BCD counter using jk ff and BCD ripple counter using jk ...are they same?
Hi ..how is the clear input have inverter (bubble form) if the zero out of NAND gate its will be logic 1 ?
BCD counter is the part of synchronous counter by m.morris mano(digital logic and computer design)
but you say it is the part of asynchronous counter.
so i want to know which is real???????? plzzz tell
+Praina Malik arey sir in this presentation explained bcd ripple counter , which is asynchronous.But there is also synchronous bcd counter.I too follow m.morris book
Praina Malik Bcd counter has both forms asynchronous as well as synchronous,both are correct
good explination man..
Rusch yozmanglar min tushinmayman
At 7:13 minute of the video why did you put the value of Qc and Qa by using a inverted NOT gate and taking the value to NAND Gate
What is the equations for j, k input? Because if i apply k-map the answers are different then =1
When to take output in counter with respect to clock pulse in negative edge triggered flip flop??
1)At the start of clock pulse or
2)At the end of clock pulse
Why cant we use Qa and Qc
the outputs have to be 1010 for not gate to reset the contour so since the outputs are 1010 does that not mean we are already showing number 10 on the display before resting???
please help Im really confused about this. Thank you all.
Can you explain any explain in which clear is applied to particular filp flop.. Eg if 4ff are there and in only 2ff clear is used.
if possible make videos on ptsp (probability theory and stochastic process) subject
in 2:09 when you are discussing positive edge trigger you are telling about the clock but not about the output clear from where you are taking the output when positive edge triggring
Is decade counter and mod 10 counter same?!
NESO the real campus
Making reset as an NAND of Qb and Qd would not show 12 and 13 ???And hence disturbing our BCD counter???bcz they are 1100 and 1101 respectively and NAND of their Qb and Qd is 1???
Muhammad Abdul Rahim I maen to say the counter will also count 12 and 13
You really work hard, I'm worried because I clear concept here but what about semester exam we've to write more and how will we write because we don't have content?
Negative egde triggering start from high to low nd in up counting we r going from low to high ...
Low to high to positive egde triggering hota h n 😣
Sir for MOD-12 asynchronous down counter.. We can it solve same as solved for MOD -6
Thank You Very Much! Your videos have helped me alot.
when to use nand gate/ and gate for clr input
u have giiven bubble at clr means if u remove bubble then u may use and?
Could you please tell me how to build a 2 digit counter which can be used to count upto 10
Hi , can u please also explain us the applications of counters ,registers n other flip flops in our daily life
AMIT KUMAR Meena they are used in computers or various devices like watches
+AMIT KUMAR Meena bro i can bulit traffic light signal by using counters
to which ff's we should give input to nand gates...you forgot to draw
is that up/down? or is it just up counter?
At time 7:11Not gate symbol is reversed and also 7:21 is also reversed. Explanation is very good.