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How to load a particular hierarchy of golden side in conformal LEC
You have to select the top module in the golden side, and keep other sub module verilog files in the same folder
Do we have any command like how we use get_cells in dc/fc shell?
@@Gnani818 you type "get_" then press tab to get suggestions in dc shell
@@VLSIToolBox i know the dc_shell commands. my question is, in conformal LEC do we have any such commands to load a hierarchy or a cell?
Why are u doing analyze setup and data path?
Analyze setup automatically resolve some unmapped points due to seq-constabt, seq merge etc
@@nikhilbathula8733 analyze setup analyze and resolve all the setup issues? Does it need svf txt or vsdc ?
If the netlist os from synopsys tool then yes a vsdc file has to be read into conformal. Conformal has an internal python script to convert vsdc file into conformal readableSvf is not required
@@nikhilbathula8733 thanks
❤
How to load a particular hierarchy of golden side in conformal LEC
You have to select the top module in the golden side, and keep other sub module verilog files in the same folder
Do we have any command like how we use get_cells in dc/fc shell?
@@Gnani818 you type "get_" then press tab to get suggestions in dc shell
@@VLSIToolBox i know the dc_shell commands. my question is, in conformal LEC do we have any such commands to load a hierarchy or a cell?
Why are u doing analyze setup and data path?
Analyze setup automatically resolve some unmapped points due to seq-constabt, seq merge etc
@@nikhilbathula8733 analyze setup analyze and resolve all the setup issues? Does it need svf txt or vsdc ?
If the netlist os from synopsys tool then yes a vsdc file has to be read into conformal. Conformal has an internal python script to convert vsdc file into conformal readable
Svf is not required
@@nikhilbathula8733 thanks
❤