Understanding Logic Equivalence Check in VLSI | What is LEC?

In this video I explain in detail about logic equivalence check (LEC). Visit my site vlsigyan.com for more.
Logic Equivalence Check, Formal Verification, Cadence Conformal LEC, Synopsys Formality.
VLSI Interview Questions

[@yrathaiah101054]

What is meant by "we can't write Boolean for Flops" and why?

[@bibekanandabora]

You can write. But the output depends on previous state. Flops are edge triggered. Clock=0 or 1, No change in output. Only transitions matter. How are you going to write this in boolean? Even if you write how are we going to check LEC then. It's not a simple combi logic. As soon as you give input you will get output without any dependecy in combi logic.

[@RandomPlayer007]

great work

[@venkatasubbareddybuvvana5029]

can you please how can we debug if lec fails,why lec fails at lockup latches generally

[@bibekanandabora]

Lockup latches are part of DFT scan chains. The output of LL goes to the scan input of the register which is blocked (by setting proper constraints) when we are verifying LEC for functional mode. So, in LEC verification these LLs are always unreachable. Now, one should not make these as LLs available for mapping in mapping stage. You can set something like, set_mapping _method -NOUNREACH in candence LEC to skip mapping of unreachable key points. If it's not getting mapped it won't come as non-eq.

[@vamshikrishna5408]

Can you say, how they will right constraints to make the extra logic as null

[@bibekanandabora]

Setting of constraints depends on design and also the comparison...as a general rule if there is any global scan enable make that zero ( considering Active logic) . It will mask all the scan paths and the scan logic won't come in LEC comparison.