PART 1: RTL SYNTHESIS USING CADENCE GENUS TOOL

[@BhushanPalkar-g9l]

Hello,
Can we generate verilog code from layout using genus synthesis tool?

[@VLSIToolBox]

No, you can generate LEF file from layout

[@LongPham-rh4cp]

Can you give me 4 input files like the example in the video? I need them to analyse and understand the tool. Thank you !

[@PrinceSaini-y7e]

can you pls share the doc file of the same , i need tuts for genus , jasper gold and xcellium cadence tools

[@VLSIToolBox]

if you have the login to cadence support you can get Rapid Adoption Kit (RAK) file for genus and other tools download it and check the manual and also script file given in the RAK

[@srikanthupputuri9290]

how can i install

[@srikanthupputuri9290]

i have cadance in my windows

[@ravindrakumar-xe7bm]

❤

[@debayanchatterjee9444]

How to install the cadence genus tool

[@VLSIToolBox]

You can contact me through mail

[@debayanchatterjee9444]

@@VLSIToolBox please provide you mail ID I will contact you for sure

[@debayanchatterjee9444]

@@VLSIToolBox or if you want I can provide you my mail ID