ขนาดวิดีโอ: 1280 X 720853 X 480640 X 360
แสดงแผงควบคุมโปรแกรมเล่น
เล่นอัตโนมัติ
เล่นใหม่
keep up the work, perfect videos.
thank you
Hello, good timeHow is the Limiter block designed in Cadence and is there a cell for Limiter in Analoglib?
Nice video. You need to get a better microphone or get closer. There is too much echo. Thanks.
🎉
How do you simulate if you have multiple modules and and have generate statements in the module
You can write a top module upon which you can instantiate the other modules and map with the top module using structural modelling.
Do you have any idea, how to simulate circuit generated using verilog code and analog circuit?.
You can do mixed mode simulation using AMS simulation process
keep up the work, perfect videos.
thank you
Hello, good time
How is the Limiter block designed in Cadence and is there a cell for Limiter in Analoglib?
Nice video. You need to get a better microphone or get closer. There is too much echo. Thanks.
🎉
How do you simulate if you have multiple modules and and have generate statements in the module
You can write a top module upon which you can instantiate the other modules and map with the top module using structural modelling.
Do you have any idea, how to simulate circuit generated using verilog code and analog circuit?.
You can do mixed mode simulation using AMS simulation process