วีดีโอ

pl , explain for me , pl

Please explain to me why CMRR is calculated by taking x0 - x1, while the formula CMRR = log20(Ad/Ac) , thanks

Fantastic tutorial ! Your step by step approach really helps to understand the workflow. One note why not use common source and drain method in layout.

do you have a video tutorial on layout for beginners ?

Great information

Hello, Can we generate verilog code from layout using genus synthesis tool?

how can i install

Sir can you make a detailed video on different types of comparator design using cadence tool which will include the sizing,noise analysis and other considerations also like metastability It will be helpful to us. 🙏🙏

Do you have any idea, how to simulate circuit generated using verilog code and analog circuit?.

Hello, good time How is the Limiter block designed in Cadence and is there a cell for Limiter in Analoglib?

Thank you 👍 ft=fh*A=(1/2*3.14*Rout*CL)*A A=Av=gm*Rout So ft=gm/2*3.14*CL, So gm=ft*2*3.14*CL.....

great sir , pls make a video on a folded cascode amplifier using Gm/id technique ....

How do you simulate if you have multiple modules and and have generate statements in the module

Great video!

Nice video for design a differential Amplifier.😊

How to load a particular hierarchy of golden side in conformal LEC

Nice demo Sir. Please tell me how to choose the drain current (ID) and transistor aspect ratio (W/L) for extracting the μCox of a transistor.

Please upload such informative videos sir🎉

Thank you very much for uploading this video , sir , great work and very nice explanation.

Nice work sir🎉

Very nice demonstration! Great 👍

Cognitive

Great

Great

Thank you so much, sir. it is very good for beginners

Why are u doing analyze setup and data path?

Can you give me 4 input files like the example in the video? I need them to analyse and understand the tool. Thank you !

Nice video sir , very informative for vlsi students...🔥

why ac analysis for psrr and not xf

Hi sir, how to view the waveform of capacitor charging?

Thanks for the video! I think that you might have chosen ABBA for randomness but since it is a current mirror, the diode transistor is better placed in the middle based on what I have seen in other explanations :)

Dear sir, How to create automatic layout from verilog code. Sir Can you make one video please

Thank you! it was very helpful

Video is very useful sir

Thankyou sir

Thankyou sir.

Good explanation and demonstration keep it up Sourav

Superb video of analog Layout design....

When I do extraction, it getting stuck at 0%, how can I debug this

can you pls share the doc file of the same , i need tuts for genus , jasper gold and xcellium cadence tools

Nice video. You need to get a better microphone or get closer. There is too much echo. Thanks.

Good explanation keep it up

Can you send the kibrary of TSMCN65 if it is possible?

👍

How to install the cadence genus tool

keep up the work, perfect videos.

🎉

love u bro from iitb

Hello brother. I am new in TSMC 65nm. Can you please tell me which model libraries should I need from global library for basic designing of PMOS, NMOS and Capacitor. I am not sure which library I should use in ADL. All the libraries are selected from my end.

❤