[Synthesis/STA] fixing setup and hold timing concepts

fixing Setup and hold violation
fix setup and hold violation

[@durgaprasadnaredla5832]

Awesome explanation....the most liked part in the lecture is explaining in practical way..

[@VLSI-learnings]

Glad to hear that

[@muthukumaranm9281]

Awesome content

[@VLSI-learnings]

Thank you

[@ShubhamPandey-bg5vx]

Gajab sir maja agya aur video daliye na

[@VLSI-learnings]

Ok

[@tausid979]

Thanks bro☺

[@VLSI-learnings]

welcome

[@poojaugare3988]

if there is no combinational circuit in between. but still we have set up time violation how to fix it by tel designer

[@omprakashchoudhary4901]

its means Hold is decided at the time of design, not after that but we can fix the setup after design completed ???

[@ankitasharma9841]

How are the rise and fall time are affected by adding the buffer?

[@VLSI-learnings]

depends on cell behaviour (lvt and svt cells)

[@aniketsangamwar1475]

can we add the buffer exact before the clock pin of capture flop that buffer will not affect the next one

[@VLSI-learnings]

Ok

[@saijagadeesh1708]

Sir , is setup and hold violations can occur in the same path ?

[@VLSI-learnings]

Yes